a46a712610
In the file `COPYING` in the coreboot repository and upstream [1]
just one space is used.
The following command was used to convert all files.
$ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/'
[1] http://www.gnu.org/licenses/gpl-2.0.txt
Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2490
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
138 lines
4.2 KiB
C
138 lines
4.2 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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static void pci_init(struct device *dev)
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{
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u16 reg16;
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u32 reg32;
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printk(BIOS_DEBUG, "Initializing ICH7 PCIe bridge.\n");
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/* Enable Bus Master */
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reg32 = pci_read_config32(dev, PCI_COMMAND);
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reg32 |= PCI_COMMAND_MASTER;
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pci_write_config32(dev, PCI_COMMAND, reg32);
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/* Set Cache Line Size to 0x10 */
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// This has no effect but the OS might expect it
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pci_write_config8(dev, 0x0c, 0x10);
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reg16 = pci_read_config16(dev, 0x3e);
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reg16 &= ~(1 << 0); /* disable parity error response */
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// reg16 &= ~(1 << 1); /* disable SERR */
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reg16 |= (1 << 2); /* ISA enable */
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pci_write_config16(dev, 0x3e, reg16);
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/* Enable IO xAPIC on this PCIe port */
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reg32 = pci_read_config32(dev, 0xd8);
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reg32 |= (1 << 7);
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pci_write_config32(dev, 0xd8, reg32);
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/* Enable Backbone Clock Gating */
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reg32 = pci_read_config32(dev, 0xe1);
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reg32 |= (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0);
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pci_write_config32(dev, 0xe1, reg32);
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#if CONFIG_MMCONF_SUPPORT
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/* Set VC0 transaction class */
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reg32 = pci_mmio_read_config32(dev, 0x114);
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reg32 &= 0xffffff00;
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reg32 |= 1;
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pci_mmio_write_config32(dev, 0x114, reg32);
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/* Mask completion timeouts */
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reg32 = pci_mmio_read_config32(dev, 0x148);
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reg32 |= (1 << 14);
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pci_mmio_write_config32(dev, 0x148, reg32);
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#else
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#error "MMIO needed for ICH7 PCIe"
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#endif
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/* Enable common clock configuration */
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// Are there cases when we don't want that?
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reg16 = pci_read_config16(dev, 0x50);
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reg16 |= (1 << 6);
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pci_write_config16(dev, 0x50, reg16);
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#ifdef EVEN_MORE_DEBUG
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reg32 = pci_read_config32(dev, 0x20);
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printk(BIOS_SPEW, " MBL = 0x%08x\n", reg32);
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reg32 = pci_read_config32(dev, 0x24);
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printk(BIOS_SPEW, " PMBL = 0x%08x\n", reg32);
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reg32 = pci_read_config32(dev, 0x28);
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printk(BIOS_SPEW, " PMBU32 = 0x%08x\n", reg32);
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reg32 = pci_read_config32(dev, 0x2c);
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printk(BIOS_SPEW, " PMLU32 = 0x%08x\n", reg32);
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#endif
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/* Clear errors in status registers */
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reg16 = pci_read_config16(dev, 0x06);
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//reg16 |= 0xf900;
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pci_write_config16(dev, 0x06, reg16);
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reg16 = pci_read_config16(dev, 0x1e);
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//reg16 |= 0xf900;
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pci_write_config16(dev, 0x1e, reg16);
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}
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static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device)
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{
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/* NOTE: This is not the default position! */
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if (!vendor || !device) {
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pci_write_config32(dev, 0x94,
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pci_read_config32(dev, 0));
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} else {
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pci_write_config32(dev, 0x94,
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((device & 0xffff) << 16) | (vendor & 0xffff));
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}
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}
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static struct pci_operations pci_ops = {
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.set_subsystem = pcie_set_subsystem,
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};
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static struct device_operations device_ops = {
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.read_resources = pci_bus_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_bus_enable_resources,
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.init = pci_init,
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.scan_bus = pci_scan_bridge,
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.ops_pci = &pci_ops,
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};
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static const unsigned short i82801gx_pcie_ids[] = {
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0x27d0, /* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */
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0x27d2, /* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */
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0x27d4, /* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */
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0x27d6, /* 82801GB/GR/GDH/GBM/GHM (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH) */
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0x27e0, /* 82801GR/GDH/GHM (ICH7R/ICH7DH/ICH7-M DH) */
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0x27e2, /* 82801GR/GDH/GHM (ICH7R/ICH7DH/ICH7-M DH) */
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0
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};
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static const struct pci_driver i82801gx_pcie __pci_driver = {
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.ops = &device_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.devices= i82801gx_pcie_ids,
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};
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