6b5bc77c9b
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
81 lines
2.1 KiB
C
81 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/mmio.h>
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#include <delay.h>
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#include <soc/addressmap.h>
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#include <soc/clk_rst.h>
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#include <soc/clock.h>
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#include <soc/nvidia/tegra/i2c.h>
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#include <soc/padconfig.h>
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#include <soc/power.h>
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#define I2C6_PADCTL 0xC001
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#define DPAUX_HYBRID_PADCTL 0x545C0124
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#define DPAUX_HYBRID_SPARE 0x545C0134
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static void enable_sor_periph_clocks(void)
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{
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clock_enable(CLK_L_HOST1X, 0, 0, 0, 0, CLK_X_DPAUX, 0);
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/* Give clocks time to stabilize. */
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udelay(IO_STABILIZATION_DELAY);
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}
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static void disable_sor_periph_clocks(void)
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{
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clock_disable(CLK_L_HOST1X, 0, 0, 0, 0, CLK_X_DPAUX, 0);
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/* Give clocks time to stabilize. */
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udelay(IO_STABILIZATION_DELAY);
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}
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static void unreset_sor_periphs(void)
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{
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clock_clr_reset(CLK_L_HOST1X, 0, 0, 0, 0, CLK_X_DPAUX, 0);
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}
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void soc_configure_i2c6pad(void)
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{
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/*
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* I2C6 on Tegra1xx requires some special init.
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* The SOR block must be unpowergated, and a couple of
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* display-based peripherals must be clocked and taken
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* out of reset so that a DPAUX register can be
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* configured to enable the I2C6 mux routing.
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* Afterwards, we can disable clocks to the display blocks
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* and put Host1X back in reset. DPAUX must remain out of
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* reset and the SOR partition must remained unpowergated.
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*/
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soc_configure_host1x();
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/* enable SOR_SAFE and DPAUX_1 clocks */
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clock_enable_y(CLK_Y_DPAUX1 | CLK_Y_SOR_SAFE);
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/* Now we can write the I2C6 mux in DPAUX */
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write32((void *)DPAUX_HYBRID_PADCTL, I2C6_PADCTL);
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/* Finally, power up the pads */
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write32((void *)DPAUX_HYBRID_SPARE, 0);
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/*
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* Delay before turning off Host1X/DPAUX clocks.
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* This delay is needed to keep the sequence from
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* hanging the system.
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*/
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udelay(CLOCK_PLL_STABLE_DELAY_US);
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/* Stop Host1X/DPAUX clocks and reset Host1X */
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disable_sor_periph_clocks();
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clock_set_reset_l(CLK_L_HOST1X);
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}
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void soc_configure_host1x(void)
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{
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power_ungate_partition(POWER_PARTID_SOR);
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/* Host1X needs a valid clock source so DPAUX can be accessed. */
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clock_configure_source(host1x, PLLP, 204000);
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enable_sor_periph_clocks();
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remove_clamps(POWER_PARTID_SOR);
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unreset_sor_periphs();
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}
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