5e9dc23120
There is one global change to pci_ids.h. The rest are changes for LX. I ran abuild and it is ok. Not all artec design changes are included as some of them would adversely affect other mainboards. Indrek will need to test. Signed-off-by: Ron Minnich Signed-off-by: Indrek Kruusa, indrek.kruusa@artecdesign.ee, artec design. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2350 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
20 lines
483 B
Text
20 lines
483 B
Text
# Config file for the olpc rev_a
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target dbe61
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mainboard artecgroup/dbe61
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# leave 128k for vsa
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option CONFIG_COMPRESSED_ROM_STREAM=0
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option ROM_SIZE=1024*256-128*1024
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option FALLBACK_SIZE=ROM_SIZE
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option DEFAULT_CONSOLE_LOGLEVEL = 11
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option MAXIMUM_CONSOLE_LOGLEVEL = 11
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romimage "fallback"
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option USE_FALLBACK_IMAGE=1
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option ROM_IMAGE_SIZE=32*1024
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option LINUXBIOS_EXTRA_VERSION=".0Fallback"
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payload /tmp/rtl8139--filo.zelf
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end
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buildrom ./linuxbios.rom ROM_SIZE "fallback"
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