0867062412
It's basically done with the following script and some manual fixup:
VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC`
for VAR in $VARS; do
find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \;
done
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
62 lines
2.1 KiB
Text
62 lines
2.1 KiB
Text
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2008 LiPPERT Embedded Computers GmbH
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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# Config file for the LiPPERT Cool RoadRunner-LX, --JR 10/2008
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# based on Config.lb for the AMD Geode LX/5536 DB800 platform.
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target roadrunner-lx
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mainboard lippert/roadrunner-lx
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# HACK to get the right TSC support.
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option CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
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option CONFIG_COMPRESSED_PAYLOAD_NRV2B = 0
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option CONFIG_COMPRESSED_PAYLOAD_LZMA = 0
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## Load payload (e.g. Linux) from IDE.
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#option CONFIG_ROM_PAYLOAD = 0
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#option CONFIG_IDE = 1
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#option CONFIG_FS_PAYLOAD = 1
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#option CONFIG_FS_EXT2 = 1
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#option CONFIG_AUTOBOOT_DELAY = 0
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#option CONFIG_AUTOBOOT_CMDLINE = "hda1:/payload.elf"
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# Leave 36k for VSA. Usually board is equipped with a 512 KB FWH (LPC) flash,
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# however it can be replaced with a 1 MB chip.
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option CONFIG_ROM_SIZE = (512 * 1024) - (36 * 1024)
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#option CONFIG_ROM_SIZE = (1024 * 1024) - (36 * 1024)
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option CONFIG_FALLBACK_SIZE = CONFIG_ROM_SIZE
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#option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 4
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#option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 4
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# Saves space on CONFIG_ROM_IMAGE_SIZE, but decompression costs a second on boot.
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option CONFIG_COMPRESS = 1
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romimage "image"
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option CONFIG_USE_FALLBACK_IMAGE = 1
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option CONFIG_ROM_IMAGE_SIZE = 64 * 1024
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option COREBOOT_EXTRA_VERSION = ".0"
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payload ../payload.elf
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# If getting payload from IDE
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# payload /dev/null
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end
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buildrom ./coreboot.rom CONFIG_ROM_SIZE "image"
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