d07ac8ee13
The `link_frequency_270_mhz` setting was originally used by the native graphics init code for Sandy/Ivy Bridge, which is long gone. The value of this information (which board had it set) is questionable. The only board that had an LVDS panel and set it to 0 was the ThinkPad L520, where native graphics init was never reported to work. Also, the native graphics init only used it for calculations, but never confi- gured the hardware to use a specific frequency. A look into the docu- mentation also doesn't reveal any straps that could be used to confi- gure it. Change-Id: Ieceaa13e4529096a8ba9036479fd84969faebd14 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39763 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
124 lines
4 KiB
Go
124 lines
4 KiB
Go
package main
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type sandybridgemc struct {
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}
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func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) {
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inteltool := ctx.InfoSource.GetInteltool()
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/* FIXME:XX Move this somewhere else. */
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MainboardIncludes = append(MainboardIncludes, "drivers/intel/gma/int15.h")
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MainboardEnable += (` /* FIXME: fix these values. */
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install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
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GMA_INT15_PANEL_FIT_DEFAULT,
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GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
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`)
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DevTree = DevTreeNode{
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Chip: "northbridge/intel/sandybridge",
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MissingParent: "northbridge",
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Comment: "FIXME: GPU registers may not always apply.",
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Registers: map[string]string{
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"gpu_dp_b_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 2) & 7),
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"gpu_dp_c_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 10) & 7),
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"gpu_dp_d_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 18) & 7),
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"gpu_panel_port_select": FormatInt32((inteltool.IGD[0xc7208] >> 30) & 3),
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"gpu_panel_power_up_delay": FormatInt32((inteltool.IGD[0xc7208] >> 16) & 0x1fff),
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"gpu_panel_power_backlight_on_delay": FormatInt32(inteltool.IGD[0xc7208] & 0x1fff),
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"gpu_panel_power_down_delay": FormatInt32((inteltool.IGD[0xc720c] >> 16) & 0x1fff),
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"gpu_panel_power_backlight_off_delay": FormatInt32(inteltool.IGD[0xc720c] & 0x1fff),
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"gpu_panel_power_cycle_delay": FormatInt32(inteltool.IGD[0xc7210] & 0xff),
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"gpu_cpu_backlight": FormatHex32(inteltool.IGD[0x48254]),
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"gpu_pch_backlight": FormatHex32((inteltool.IGD[0xc8254] >> 16) * 0x10001),
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"gfx.use_spread_spectrum_clock": FormatBool((inteltool.IGD[0xc6200]>>12)&1 != 0),
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},
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Children: []DevTreeNode{
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{
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Chip: "cpu_cluster",
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Dev: 0,
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Children: []DevTreeNode{
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{
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Chip: "cpu/intel/model_206ax",
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Comment: "FIXME: check all registers",
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Registers: map[string]string{
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/* FIXME:XX hardcoded. */
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"c1_acpower": "1",
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"c2_acpower": "3",
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"c3_acpower": "5",
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"c1_battery": "1",
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"c2_battery": "3",
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"c3_battery": "5",
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},
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Children: []DevTreeNode{
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{
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Chip: "lapic",
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Dev: 0,
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},
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{
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Chip: "lapic",
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Dev: 0xacac,
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Disabled: true,
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},
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},
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},
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},
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},
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{
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Chip: "domain",
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Dev: 0,
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PCIController: true,
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ChildPCIBus: 0,
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PCISlots: []PCISlot{
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PCISlot{PCIAddr: PCIAddr{Dev: 0x0, Func: 0}, writeEmpty: true, additionalComment: "Host bridge"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x1, Func: 0}, writeEmpty: true, additionalComment: "PEG"},
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PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, additionalComment: "iGPU"},
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},
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},
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},
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}
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PutPCIDev(addr, "Host bridge")
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/* FIXME:XX some configs are unsupported. */
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KconfigBool["NORTHBRIDGE_INTEL_SANDYBRIDGE"] = true
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KconfigBool["USE_NATIVE_RAMINIT"] = true
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KconfigBool["INTEL_INT15"] = true
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KconfigBool["HAVE_ACPI_TABLES"] = true
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KconfigBool["HAVE_ACPI_RESUME"] = true
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KconfigInt["MAX_CPUS"] = 8
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DSDTIncludes = append(DSDTIncludes, DSDTInclude{
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File: "cpu/intel/common/acpi/cpu.asl",
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})
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DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{
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File: "northbridge/intel/sandybridge/acpi/sandybridge.asl",
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}, DSDTInclude{
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File: "drivers/intel/gma/acpi/default_brightness_levels.asl",
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})
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}
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func init() {
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RegisterPCI(0x8086, 0x0100, sandybridgemc{})
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RegisterPCI(0x8086, 0x0104, sandybridgemc{})
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RegisterPCI(0x8086, 0x0150, sandybridgemc{})
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RegisterPCI(0x8086, 0x0154, sandybridgemc{})
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RegisterPCI(0x8086, 0x0158, sandybridgemc{})
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for _, id := range []uint16{
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0x0102, 0x0106, 0x010a,
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0x0112, 0x0116, 0x0122, 0x0126,
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0x0152, 0x0156, 0x0162, 0x0166,
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} {
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RegisterPCI(0x8086, id, GenericVGA{GenericPCI{}})
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}
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/* PCIe bridge */
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for _, id := range []uint16{
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0x0101, 0x0105, 0x0109, 0x010d,
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0x0151, 0x0155, 0x0159, 0x015d,
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} {
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RegisterPCI(0x8086, id, GenericPCI{})
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}
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}
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