coreboot-kgpe-d16

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Duncan Laurie 0920915bca ELOG: Support GSMI in CPT/PPT southbridge SMI handler In order to support the GSMI interface the SMI handler needs to find and use the state save area from the same CPU that initiated the SMI. In this case it is a synchronous SMI resulting form an IO write to port 0xB2. To find the right CPU state save area iterate over the region until the "IO Misc Info" field reports the expected value and then proceed to use that state save area. This is needed because the coreboot SMI handler only executes on one core, and that core is non-deterministic. It is likely that the core executing the C SMM handler is not the same one that actually did the IO write to 0xB2 and generated the SMI. The GSMI parameter buffer is passed as a pointer to EBX in the tate save area, and the GSMI command is extracted from EAX before it is used as the return value. This interface is tested by enabling CONFIG_GOOGLE_GSMI in the kernel and generating events and verifying that they end up in the event log. 159 \| 2012-06-23 16:22:45 \| Kernl Event \| Clean Shutdown 184 \| 2012-06-23 17:14:05 \| Kernl Event \| Oops 185 \| 2012-06-23 17:14:05 \| Kernl Event \| Panic Change-Id: Ic121ea69e9f50c88467c435e095c3e3629989806 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1317 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>		2012-07-26 20:28:38 +02:00
3rdparty@f933fda790	Finally update 3rdparty	2012-07-19 13:58:02 +02:00
documentation	Whitespace/typo/cosmetic fixes (trivial).	2010-09-23 18:48:27 +00:00
payloads	libpayload: Add reset function for OHCI USB driver	2012-07-12 10:00:17 +02:00
src	ELOG: Support GSMI in CPT/PPT southbridge SMI handler	2012-07-26 20:28:38 +02:00
util	ifdtool: Use perror for file write errors	2012-07-24 10:13:33 +02:00
.gitignore	romcc: kill gcc warnings and .gitignore generated files	2012-02-07 22:34:42 +01:00
.gitmodules	Add 3rdparty as submodule	2012-05-01 00:08:37 +02:00
COPYING	update license template.	2006-08-12 22:03:36 +00:00
Makefile	Keep cscope.out when distclean.	2012-03-31 12:06:10 +02:00
Makefile.inc	abuild: Build boards in parallel if possible	2012-05-10 22:11:16 +02:00
README	Update README with newer version of the text from the web page	2011-06-15 10:16:33 +02:00

README

-------------------------------------------------------------------------------
coreboot README
-------------------------------------------------------------------------------

coreboot is a Free Software project aimed at replacing the proprietary BIOS
(firmware) found in most computers.  coreboot performs a little bit of
hardware initialization and then executes additional boot logic, called a
payload.

With the separation of hardware initialization and later boot logic,
coreboot can scale from specialized applications that run directly
firmware, run operating systems in flash, load custom
bootloaders, or implement firmware standards, like PC BIOS services or
UEFI. This allows for systems to only include the features necessary
in the target application, reducing the amount of code and flash space
required.

coreboot was formerly known as LinuxBIOS.


Payloads
--------

After the basic initialization of the hardware has been performed, any
desired "payload" can be started by coreboot.

See http://www.coreboot.org/Payloads for a list of supported payloads.


Supported Hardware
------------------

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

 * http://www.coreboot.org/Supported_Motherboards
 * http://www.coreboot.org/Supported_Chipsets_and_Devices


Build Requirements
------------------

 * gcc / g++
 * make

Optional:

 * doxygen (for generating/viewing documentation)
 * iasl (for targets with ACPI support)
 * gdb (for better debugging facilities on some targets)
 * ncurses (for 'make menuconfig')
 * flex and bison (for regenerating parsers)


Building coreboot
-----------------

Please consult http://www.coreboot.org/Build_HOWTO for details.


Testing coreboot Without Modifying Your Hardware
------------------------------------------------

If you want to test coreboot without any risks before you really decide
to use it on your hardware, you can use the QEMU system emulator to run
coreboot virtually in QEMU.

Please see http://www.coreboot.org/QEMU for details.


Website and Mailing List
------------------------

Further details on the project, a FAQ, many HOWTOs, news, development
guidelines and more can be found on the coreboot website:

  http://www.coreboot.org

You can contact us directly on the coreboot mailing list:

  http://www.coreboot.org/Mailinglist


Copyright and License
---------------------

The copyright on coreboot is owned by quite a large number of individual
developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL).
Some files are licensed under the "GPL (version 2, or any later version)",
and some files are licensed under the "GPL, version 2". For some parts, which
were derived from other projects, other (GPL-compatible) licenses may apply.
Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.