092cac58de
This patch makes some slight changes to the exception hook interface. The old code provides a different handler hook for every exception type... however, in practice all those hook functions often need to look very similar, so this creates more boilerplate than it removes. The new interface just allows for a single hook with the exception type passed as an argument, and the consumer can signal whether the exception was handled through the return value. (Right now this still only supports one consumer, but it could easily be extended to walk through a list of hooks if the need arises.) Also move the excepton state from an argument to a global. This avoids a lot of boilerplate since some consumers need to change the state from many places, so they would have to pass the same pointer around many times. It also removes the false suggestion that the exception state was not global and you could have multiple copies of it (which the exception core doesn't support for any architecture). On the ARM side, the exception state is separated from the exception stack for easier access. (This requires some assembly changes, and I threw in a few comments and corrected the immediate sigils from '$' to the official '#' while I'm there.) Since the exception state is now both stored and loaded through an indirection pointer, this allows for some very limited reentrance (you could point it to a different struct while handling an exception, and while you still won't be able to return to the outer-level exception from there, you could at least swap out the pointer and return back to System Mode in one go). BUG=chrome-os-partner:18390 TEST=Made sure normal exceptions still get dumped correctly on both archs. Original-Change-Id: I5d9a934fab7c14ccb2c9d7ee4b3465c825521fa2 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/202562 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit 97542110f0b385b9b8d89675866e65db8ca32aeb) Signed-off-by: Marc Jones <marc.jones@se-eng.com> *** Squashed to prevent build failures. *** libpayload: align arm64 with new exception handling model The exception handling was previously updated, however the arm64 changes raced with hat one. Make the arm64 align with the new model. Without these changes compilation will fail. BUG=None BRANCH=None TEST=Can build libpayload for rush. Original-Change-Id: I320b39a57b985d1f87446ea7757955664f8dba8f Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/204402 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 0080df41b311ef20f9214b386fa4e38ee54aa1a1) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I9a0bb3848cf5286f9f4bb08172a9f4a15278348e Reviewed-on: http://review.coreboot.org/8117 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> |
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| 3rdparty@a8b0c52850 | ||
| documentation | ||
| payloads | ||
| src | ||
| util | ||
| .gitignore | ||
| .gitmodules | ||
| .gitreview | ||
| COPYING | ||
| Makefile | ||
| Makefile.inc | ||
| README | ||
| toolchain.inc | ||
README
------------------------------------------------------------------------------- coreboot README ------------------------------------------------------------------------------- coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload. With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required. coreboot was formerly known as LinuxBIOS. Payloads -------- After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot. See http://www.coreboot.org/Payloads for a list of supported payloads. Supported Hardware ------------------ coreboot supports a wide range of chipsets, devices, and mainboards. For details please consult: * http://www.coreboot.org/Supported_Motherboards * http://www.coreboot.org/Supported_Chipsets_and_Devices Build Requirements ------------------ * gcc / g++ * make Optional: * doxygen (for generating/viewing documentation) * iasl (for targets with ACPI support) * gdb (for better debugging facilities on some targets) * ncurses (for 'make menuconfig') * flex and bison (for regenerating parsers) Building coreboot ----------------- Please consult http://www.coreboot.org/Build_HOWTO for details. Testing coreboot Without Modifying Your Hardware ------------------------------------------------ If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU. Please see http://www.coreboot.org/QEMU for details. Website and Mailing List ------------------------ Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website: http://www.coreboot.org You can contact us directly on the coreboot mailing list: http://www.coreboot.org/Mailinglist Copyright and License --------------------- The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details. coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details. This makes the resulting coreboot images licensed under the GPL, version 2.