0946ec37aa
Provide a common romstage implementation for the Intel SOCs. BRANCH=none BUG=None TEST=Build for Braswell Change-Id: I80f5f8f0f36e9023117b07d4af5c806fff8157b6 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10050 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
19 lines
770 B
Makefile
19 lines
770 B
Makefile
ifeq ($(CONFIG_SOC_INTEL_COMMON),y)
|
|
|
|
romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c
|
|
romstage-$(CONFIG_SOC_INTEL_COMMON_FSP_RAM_INIT) += raminit.c
|
|
romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
|
|
romstage-$(CONFIG_SOC_INTEL_COMMON_FSP_ROMSTAGE) += romstage.c
|
|
romstage-$(CONFIG_SOC_INTEL_COMMON_STACK) += stack.c
|
|
romstage-$(CONFIG_SOC_INTEL_COMMON_STAGE_CACHE) += stage_cache.c
|
|
romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += util.c
|
|
|
|
ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp_ramstage.c
|
|
ramstage-y += hda_verb.c
|
|
ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c
|
|
ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c
|
|
ramstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
|
|
ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += util.c
|
|
ramstage-$(CONFIG_GOP_SUPPORT) += vbt.c
|
|
|
|
endif
|