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Sridahr Siricilla 096ce1444e soc/intel/alderlake: Support PCIe hardware compliance test mode
The validation process verifies that hardware components comply with
the standard hardware specifications. For instance, PCI express
implementation must comply with the hardware PCIe specification
requirements: Electrical, Configuration, Link Protocol and Transaction
Protocol. To perform these tests the hardware must be configured in a
particular state: some feature related to power management need to be
turned off, hot plug should be enabled...

This patch sets the appropriate FSP Updateable Product Data flags to
get the hardware in the proper configuration:
- Enable PCIe hotplug on all ports
- Set clock sources to run free
- Set the FSP compliance test mode flag

BUG=b:235863379
TEST=Compilation with and without the flag
     Verify code path with instrumentation

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: Ic07b9276121dfbd273a8f63a1f775ddbd3566884
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-07-14 23:12:36 +00:00
3rdparty 3rdparty/blobs: Advance submodule pointer 2022-07-07 15:53:33 +00:00
Documentation Remove executable flag from source codes and text files 2022-07-14 12:46:07 +00:00
LICENSES treewide: Unify Google branding 2022-07-04 14:02:26 +00:00
configs configs: Update prodrive hermes 2022-07-14 12:48:20 +00:00
payloads Remove executable flag from source codes and text files 2022-07-14 12:46:07 +00:00
spd mb/google/volteer/eldrid: Add new DDR4 part H5AG36EXNDX019 2022-07-14 23:11:19 +00:00
src soc/intel/alderlake: Support PCIe hardware compliance test mode 2022-07-14 23:12:36 +00:00
tests tests: Adjust the order of header files to include 2022-07-14 23:08:24 +00:00
util commonlib: Substitude macro "__unused" in compiler.h 2022-07-14 23:08:09 +00:00
.checkpatch.conf checkpatch.conf: Disable gerrit change ID for coreboot 2022-04-12 20:39:50 +00:00
.clang-format
.editorconfig
.gitignore .gitignore: Ignore .cache directory & compile_commands.json 2022-07-06 00:33:48 +00:00
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AUTHORS
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MAINTAINERS MAINTAINERS: Add Maintainers for Intel Elkhart Lake SoC 2022-06-05 21:07:26 +00:00
Makefile Makefile: Update error if building real-all when NOCOMPILE is set 2022-06-28 02:34:44 +00:00
Makefile.inc Makefile.inc: objcopy extracts a wrong section of cbfs_master_header 2022-07-14 12:45:03 +00:00
README.md Treewide: Remove doxygen config files and targets 2022-05-28 01:24:51 +00:00
gnat.adc
toolchain.inc build system: immediately report what users are supposed to look into 2021-10-18 16:39:25 +00:00

README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.