930 lines
21 KiB
Plaintext
930 lines
21 KiB
Plaintext
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2009-2010 coresystems GmbH
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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mainmenu "Coreboot Configuration"
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menu "General setup"
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config EXPERT
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bool "Expert mode"
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help
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This allows you to select certain advanced configuration options.
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Warning: Only enable this option if you really know what you are
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doing! You have been warned!
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config LOCALVERSION
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string "Local version string"
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help
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Append an extra string to the end of the coreboot version.
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This can be useful if, for instance, you want to append the
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respective board's hostname or some other identifying string to
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the coreboot version number, so that you can easily distinguish
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boot logs of different boards from each other.
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config CBFS_PREFIX
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string "CBFS prefix to use"
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default "fallback"
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help
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Select the prefix to all files put into the image. It's "fallback"
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by default, "normal" is a common alternative.
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choice
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prompt "Compiler"
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default COMPILER_GCC
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help
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This option allows you to select the compiler used for building
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coreboot.
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config COMPILER_GCC
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bool "GCC"
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config COMPILER_LLVM_CLANG
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bool "LLVM/clang"
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endchoice
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config SCANBUILD_ENABLE
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bool "Build with scan-build for static analysis"
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default n
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help
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Changes the build process to scan-build is used.
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Requires scan-build in path.
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config SCANBUILD_REPORT_LOCATION
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string "Directory to put scan-build report in"
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default ""
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depends on SCANBUILD_ENABLE
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help
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Where the scan-build report should be stored
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config CCACHE
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bool "ccache"
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default n
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help
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Enables the use of ccache for faster builds.
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Requires ccache in path.
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config SCONFIG_GENPARSER
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bool "Generate SCONFIG parser using flex and bison"
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default n
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depends on EXPERT
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help
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Enable this option if you are working on the sconfig
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device tree parser and made changes to sconfig.l and
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sconfig.y.
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Otherwise, say N.
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config USE_OPTION_TABLE
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bool "Use CMOS for configuration values"
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default n
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depends on HAVE_OPTION_TABLE
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help
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Enable this option if coreboot shall read options from the "CMOS"
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NVRAM instead of using hard coded values.
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config COMPRESS_RAMSTAGE
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bool "Compress ramstage with LZMA"
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default y
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help
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Compress ramstage to save memory in the flash image. Note
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that decompression might slow down booting if the boot flash
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is connected through a slow Link (i.e. SPI)
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config INCLUDE_CONFIG_FILE
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bool "Include the coreboot config file into the ROM image"
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default y
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help
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Include in CBFS the coreboot config file that was used to compile the ROM image
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endmenu
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source src/mainboard/Kconfig
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# This option is used to set the architecture of a mainboard to X86.
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# It is usually set in mainboard/*/Kconfig.
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config ARCH_X86
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bool
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default n
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if ARCH_X86
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source src/arch/x86/Kconfig
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endif
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menu "Chipset"
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comment "CPU"
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source src/cpu/Kconfig
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comment "Northbridge"
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source src/northbridge/Kconfig
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comment "Southbridge"
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source src/southbridge/Kconfig
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comment "Super I/O"
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source src/superio/Kconfig
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comment "Devices"
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source src/devices/Kconfig
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comment "Embedded Controllers"
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source src/ec/Kconfig
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endmenu
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menu "Generic Drivers"
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source src/drivers/Kconfig
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endmenu
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config PCI_BUS_SEGN_BITS
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int
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default 0
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config PCI_ROM_RUN
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bool
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default n
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config HEAP_SIZE
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hex
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default 0x4000
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config MAX_CPUS
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int
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default 1
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config MMCONF_SUPPORT_DEFAULT
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bool
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default n
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config MMCONF_SUPPORT
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bool
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default n
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source src/console/Kconfig
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# This should default to N and be set by SuperI/O drivers that have an UART
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config HAVE_UART_IO_MAPPED
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bool
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default y
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config HAVE_UART_MEMORY_MAPPED
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bool
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default n
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config HAVE_ACPI_RESUME
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bool
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default n
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config HAVE_ACPI_SLIC
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bool
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default n
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config ACPI_SSDTX_NUM
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int
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default 0
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config HAVE_HARD_RESET
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bool
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default y if BOARD_HAS_HARD_RESET
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default n
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help
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This variable specifies whether a given board has a hard_reset
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function, no matter if it's provided by board code or chipset code.
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config HAVE_INIT_TIMER
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bool
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default n if UDELAY_IO
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default y
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config HAVE_MAINBOARD_RESOURCES
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bool
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default n
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config USE_OPTION_TABLE
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bool
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default n
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config HAVE_OPTION_TABLE
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bool
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default n
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help
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This variable specifies whether a given board has a cmos.layout
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file containing NVRAM/CMOS bit definitions.
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It defaults to 'n' but can be selected in mainboard/*/Kconfig.
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config PIRQ_ROUTE
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bool
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default n
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config HAVE_SMI_HANDLER
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bool
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default n
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config PCI_IO_CFG_EXT
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bool
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default n
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config IOAPIC
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bool
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default n
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# TODO: Can probably be removed once all chipsets have kconfig options for it.
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config VIDEO_MB
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int
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default 0
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config USE_WATCHDOG_ON_BOOT
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bool
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default n
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config VGA
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bool
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default n
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help
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Build board-specific VGA code.
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config GFXUMA
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bool
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default n
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help
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Enable Unified Memory Architecture for graphics.
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# TODO
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# menu "Drivers"
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#
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# endmenu
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config HAVE_ACPI_TABLES
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bool
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help
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This variable specifies whether a given board has ACPI table support.
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It is usually set in mainboard/*/Kconfig.
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Whether or not the ACPI tables are actually generated by coreboot
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is configurable by the user via GENERATE_ACPI_TABLES.
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config HAVE_MP_TABLE
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bool
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help
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This variable specifies whether a given board has MP table support.
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It is usually set in mainboard/*/Kconfig.
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Whether or not the MP table is actually generated by coreboot
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is configurable by the user via GENERATE_MP_TABLE.
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config HAVE_PIRQ_TABLE
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bool
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help
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This variable specifies whether a given board has PIRQ table support.
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It is usually set in mainboard/*/Kconfig.
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Whether or not the PIRQ table is actually generated by coreboot
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is configurable by the user via GENERATE_PIRQ_TABLE.
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#These Options are here to avoid "undefined" warnings.
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#The actual selection and help texts are in the following menu.
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config GENERATE_ACPI_TABLES
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bool
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default HAVE_ACPI_TABLES
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config GENERATE_MP_TABLE
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bool
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default HAVE_MP_TABLE
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config GENERATE_PIRQ_TABLE
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bool
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default HAVE_PIRQ_TABLE
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config GENERATE_SMBIOS_TABLES
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bool
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default y
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menu "System tables"
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config WRITE_HIGH_TABLES
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bool "Write 'high' tables to avoid being overwritten in F segment"
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default y
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config MULTIBOOT
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bool "Generate Multiboot tables (for GRUB2)"
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default y
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config GENERATE_ACPI_TABLES
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depends on HAVE_ACPI_TABLES
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bool "Generate ACPI tables"
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default y
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help
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Generate ACPI tables for this board.
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If unsure, say Y.
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config GENERATE_MP_TABLE
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depends on HAVE_MP_TABLE
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bool "Generate an MP table"
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default y
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help
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Generate an MP table (conforming to the Intel MultiProcessor
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specification 1.4) for this board.
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If unsure, say Y.
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config GENERATE_PIRQ_TABLE
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depends on HAVE_PIRQ_TABLE
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bool "Generate a PIRQ table"
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default y
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help
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Generate a PIRQ table for this board.
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If unsure, say Y.
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config GENERATE_SMBIOS_TABLES
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depends on ARCH_X86
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bool "Generate SMBIOS tables"
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default y
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help
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Generate SMBIOS tables for this board.
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If unsure, say Y.
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endmenu
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menu "Payload"
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choice
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prompt "Add a payload"
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default PAYLOAD_NONE if !ARCH_X86
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default PAYLOAD_SEABIOS if ARCH_X86
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config PAYLOAD_NONE
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bool "None"
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help
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Select this option if you want to create an "empty" coreboot
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ROM image for a certain mainboard, i.e. a coreboot ROM image
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which does not yet contain a payload.
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For such an image to be useful, you have to use 'cbfstool'
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to add a payload to the ROM image later.
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config PAYLOAD_ELF
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bool "An ELF executable payload"
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help
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Select this option if you have a payload image (an ELF file)
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which coreboot should run as soon as the basic hardware
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initialization is completed.
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You will be able to specify the location and file name of the
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payload image later.
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config PAYLOAD_SEABIOS
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bool "SeaBIOS"
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depends on ARCH_X86
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help
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Select this option if you want to build a coreboot image
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with a SeaBIOS payload. If you don't know what this is
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about, just leave it enabled.
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See http://coreboot.org/Payloads for more information.
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config PAYLOAD_FILO
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bool "FILO"
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help
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Select this option if you want to build a coreboot image
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with a FILO payload. If you don't know what this is
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about, just leave it enabled.
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See http://coreboot.org/Payloads for more information.
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endchoice
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choice
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prompt "SeaBIOS version"
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default SEABIOS_STABLE
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depends on PAYLOAD_SEABIOS
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config SEABIOS_STABLE
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bool "stable"
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help
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Stable SeaBIOS version
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config SEABIOS_MASTER
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bool "master"
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help
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Newest SeaBIOS version
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endchoice
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choice
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prompt "FILO version"
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default FILO_STABLE
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depends on PAYLOAD_FILO
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config FILO_STABLE
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bool "0.6.0"
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help
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Stable FILO version
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config FILO_MASTER
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bool "HEAD"
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help
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Newest FILO version
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endchoice
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config PAYLOAD_FILE
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string "Payload path and filename"
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depends on PAYLOAD_ELF
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default "payload.elf"
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help
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The path and filename of the ELF executable file to use as payload.
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config PAYLOAD_FILE
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depends on PAYLOAD_SEABIOS
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default "payloads/external/SeaBIOS/seabios/out/bios.bin.elf"
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config PAYLOAD_FILE
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depends on PAYLOAD_FILO
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default "payloads/external/FILO/filo/build/filo.elf"
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# TODO: Defined if no payload? Breaks build?
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config COMPRESSED_PAYLOAD_LZMA
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bool "Use LZMA compression for payloads"
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default y
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depends on PAYLOAD_ELF || PAYLOAD_SEABIOS || PAYLOAD_FILO
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help
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In order to reduce the size payloads take up in the ROM chip
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coreboot can compress them using the LZMA algorithm.
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config COMPRESSED_PAYLOAD_NRV2B
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bool
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default n
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endmenu
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menu "VGA BIOS"
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config VGA_BIOS
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bool "Add a VGA BIOS image"
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help
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Select this option if you have a VGA BIOS image that you would
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like to add to your ROM.
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You will be able to specify the location and file name of the
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image later.
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config VGA_BIOS_FILE
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string "VGA BIOS path and filename"
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depends on VGA_BIOS
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default "vgabios.bin"
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help
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The path and filename of the file to use as VGA BIOS.
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config VGA_BIOS_ID
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string "VGA device PCI IDs"
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depends on VGA_BIOS
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default "1106,3230"
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help
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The comma-separated PCI vendor and device ID that would associate
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your VGA BIOS to your video card.
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Example: 1106,3230
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In the above example 1106 is the PCI vendor ID (in hex, but without
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the "0x" prefix) and 3230 specifies the PCI device ID of the
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video card (also in hex, without "0x" prefix).
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config INTEL_MBI
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bool "Add an MBI image"
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depends on NORTHBRIDGE_INTEL_I82830
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help
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Select this option if you have an Intel MBI image that you would
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like to add to your ROM.
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You will be able to specify the location and file name of the
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image later.
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config MBI_FILE
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string "Intel MBI path and filename"
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depends on INTEL_MBI
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default "mbi.bin"
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help
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The path and filename of the file to use as VGA BIOS.
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endmenu
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menu "Display"
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depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE
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config FRAMEBUFFER_SET_VESA_MODE
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prompt "Set VESA framebuffer mode"
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bool
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depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE
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help
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Set VESA framebuffer mode (needed for bootsplash)
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# TODO: Turn this into a "choice".
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config FRAMEBUFFER_VESA_MODE
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prompt "VESA framebuffer video mode"
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hex
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default 0x117
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depends on FRAMEBUFFER_SET_VESA_MODE
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help
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This option sets the resolution used for the coreboot framebuffer (and
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bootsplash screen). Set to 0x117 for 1024x768x16. A diligent soul will
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some day make this a "choice".
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config FRAMEBUFFER_KEEP_VESA_MODE
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prompt "Keep VESA framebuffer"
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bool
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depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE
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help
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This option keeps the framebuffer mode set after coreboot finishes
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execution. If this option is enabled, coreboot will pass a
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framebuffer entry in its coreboot table and the payload will need a
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framebuffer driver. If this option is disabled, coreboot will switch
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back to text mode before handing control to a payload.
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config BOOTSPLASH
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prompt "Show graphical bootsplash"
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bool
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depends on FRAMEBUFFER_SET_VESA_MODE
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help
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This option shows a graphical bootsplash screen. The grapics are
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loaded from the CBFS file bootsplash.jpg.
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config BOOTSPLASH_FILE
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string "Bootsplash path and filename"
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depends on BOOTSPLASH
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default "bootsplash.jpg"
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help
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The path and filename of the file to use as graphical bootsplash
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screen. The file format has to be jpg.
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endmenu
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menu "Debugging"
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# TODO: Better help text and detailed instructions.
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config GDB_STUB
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bool "GDB debugging support"
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default y
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help
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If enabled, you will be able to set breakpoints for gdb debugging.
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See src/arch/x86/lib/c_start.S for details.
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config HAVE_DEBUG_RAM_SETUP
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def_bool n
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config DEBUG_RAM_SETUP
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bool "Output verbose RAM init debug messages"
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default n
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depends on HAVE_DEBUG_RAM_SETUP
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help
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This option enables additional RAM init related debug messages.
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It is recommended to enable this when debugging issues on your
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board which might be RAM init related.
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Note: This option will increase the size of the coreboot image.
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If unsure, say N.
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config HAVE_DEBUG_CAR
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def_bool n
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config DEBUG_CAR
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def_bool n
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depends on HAVE_DEBUG_CAR
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if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
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# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
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# printk(BIOS_DEBUG, ...) calls.
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config DEBUG_CAR
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bool "Output verbose Cache-as-RAM debug messages"
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default n
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depends on HAVE_DEBUG_CAR
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help
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This option enables additional CAR related debug messages.
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endif
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config DEBUG_PIRQ
|
|
bool "Check PIRQ table consistency"
|
|
default n
|
|
depends on GENERATE_PIRQ_TABLE
|
|
help
|
|
If unsure, say N.
|
|
|
|
config HAVE_DEBUG_SMBUS
|
|
def_bool n
|
|
|
|
config DEBUG_SMBUS
|
|
bool "Output verbose SMBus debug messages"
|
|
default n
|
|
depends on HAVE_DEBUG_SMBUS
|
|
help
|
|
This option enables additional SMBus (and SPD) debug messages.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config DEBUG_SMI
|
|
bool "Output verbose SMI debug messages"
|
|
default n
|
|
depends on HAVE_SMI_HANDLER
|
|
help
|
|
This option enables additional SMI related debug messages.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config DEBUG_SMM_RELOCATION
|
|
bool "Debug SMM relocation code"
|
|
default n
|
|
depends on HAVE_SMI_HANDLER
|
|
help
|
|
This option enables additional SMM handler relocation related
|
|
debug messages.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config DEBUG_MALLOC
|
|
def_bool n
|
|
|
|
# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
|
|
# printk(BIOS_DEBUG, ...) calls.
|
|
if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
|
|
config DEBUG_MALLOC
|
|
bool "Output verbose malloc debug messages"
|
|
default n
|
|
help
|
|
This option enables additional malloc related debug messages.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
endif
|
|
|
|
config DEBUG_ACPI
|
|
def_bool n
|
|
|
|
# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
|
|
# printk(BIOS_DEBUG, ...) calls.
|
|
if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
|
|
config DEBUG_ACPI
|
|
bool "Output verbose ACPI debug messages"
|
|
default n
|
|
help
|
|
This option enables additional ACPI related debug messages.
|
|
|
|
Note: This option will slightly increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
endif
|
|
|
|
config REALMODE_DEBUG
|
|
def_bool n
|
|
depends on PCI_OPTION_ROM_RUN_REALMODE
|
|
|
|
if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
|
|
# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
|
|
# printk(BIOS_DEBUG, ...) calls.
|
|
config REALMODE_DEBUG
|
|
bool "Enable debug messages for option ROM execution"
|
|
default n
|
|
depends on PCI_OPTION_ROM_RUN_REALMODE
|
|
help
|
|
This option enables additional x86emu related debug messages.
|
|
|
|
Note: This option will increase the time to emulate a ROM.
|
|
|
|
If unsure, say N.
|
|
endif
|
|
|
|
config X86EMU_DEBUG
|
|
bool "Output verbose x86emu debug messages"
|
|
default n
|
|
depends on PCI_OPTION_ROM_RUN_YABEL
|
|
help
|
|
This option enables additional x86emu related debug messages.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config X86EMU_DEBUG_JMP
|
|
bool "Trace JMP/RETF"
|
|
default n
|
|
depends on X86EMU_DEBUG
|
|
help
|
|
Print information about JMP and RETF opcodes from x86emu.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config X86EMU_DEBUG_TRACE
|
|
bool "Trace all opcodes"
|
|
default n
|
|
depends on X86EMU_DEBUG
|
|
help
|
|
Print _all_ opcodes that are executed by x86emu.
|
|
|
|
WARNING: This will produce a LOT of output and take a long time.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config X86EMU_DEBUG_PNP
|
|
bool "Log Plug&Play accesses"
|
|
default n
|
|
depends on X86EMU_DEBUG
|
|
help
|
|
Print Plug And Play accesses made by option ROMs.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config X86EMU_DEBUG_DISK
|
|
bool "Log Disk I/O"
|
|
default n
|
|
depends on X86EMU_DEBUG
|
|
help
|
|
Print Disk I/O related messages.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config X86EMU_DEBUG_PMM
|
|
bool "Log PMM"
|
|
default n
|
|
depends on X86EMU_DEBUG
|
|
help
|
|
Print messages related to POST Memory Manager (PMM).
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
config X86EMU_DEBUG_VBE
|
|
bool "Debug VESA BIOS Extensions"
|
|
default n
|
|
depends on X86EMU_DEBUG
|
|
help
|
|
Print messages related to VESA BIOS Extension (VBE) functions.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config X86EMU_DEBUG_INT10
|
|
bool "Redirect INT10 output to console"
|
|
default n
|
|
depends on X86EMU_DEBUG
|
|
help
|
|
Let INT10 (i.e. character output) calls print messages to debug output.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config X86EMU_DEBUG_INTERRUPTS
|
|
bool "Log intXX calls"
|
|
default n
|
|
depends on X86EMU_DEBUG
|
|
help
|
|
Print messages related to interrupt handling.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config X86EMU_DEBUG_CHECK_VMEM_ACCESS
|
|
bool "Log special memory accesses"
|
|
default n
|
|
depends on X86EMU_DEBUG
|
|
help
|
|
Print messages related to accesses to certain areas of the virtual
|
|
memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config X86EMU_DEBUG_MEM
|
|
bool "Log all memory accesses"
|
|
default n
|
|
depends on X86EMU_DEBUG
|
|
help
|
|
Print memory accesses made by option ROM.
|
|
Note: This also includes accesses to fetch instructions.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config X86EMU_DEBUG_IO
|
|
bool "Log IO accesses"
|
|
default n
|
|
depends on X86EMU_DEBUG
|
|
help
|
|
Print I/O accesses made by option ROM.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config LLSHELL
|
|
bool "Built-in low-level shell"
|
|
default n
|
|
help
|
|
If enabled, you will have a low level shell to examine your machine.
|
|
Put llshell() in your (romstage) code to start the shell.
|
|
See src/arch/x86/llshell/llshell.inc for details.
|
|
|
|
config TRACE
|
|
bool "Trace function calls"
|
|
default n
|
|
help
|
|
If enabled, every function will print information to console once
|
|
the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
|
|
the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
|
|
of calling function. Please note some printk releated functions
|
|
are omitted from trace to have good looking console dumps.
|
|
endmenu
|
|
|
|
config LIFT_BSP_APIC_ID
|
|
bool
|
|
default n
|
|
|
|
# These probably belong somewhere else, but they are needed somewhere.
|
|
config AP_CODE_IN_CAR
|
|
bool
|
|
default n
|
|
|
|
config RAMINIT_SYSINFO
|
|
bool
|
|
default n
|
|
|
|
config ENABLE_APIC_EXT_ID
|
|
bool
|
|
default n
|
|
|
|
config WARNINGS_ARE_ERRORS
|
|
bool
|
|
default y
|
|
|
|
config ID_SECTION_OFFSET
|
|
hex
|
|
default 0x10
|
|
|
|
# The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
|
|
# POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
|
|
# mutually exclusive. One of these options must be selected in the
|
|
# mainboard Kconfig if the chipset supports enabling and disabling of
|
|
# the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
|
|
# in mainboard/Kconfig to know if the button should be enabled or not.
|
|
|
|
config POWER_BUTTON_DEFAULT_ENABLE
|
|
def_bool n
|
|
help
|
|
Select when the board has a power button which can optionally be
|
|
disabled by the user.
|
|
|
|
config POWER_BUTTON_DEFAULT_DISABLE
|
|
def_bool n
|
|
help
|
|
Select when the board has a power button which can optionally be
|
|
enabled by the user, e.g. when the board ships with a jumper over
|
|
the power switch contacts.
|
|
|
|
config POWER_BUTTON_FORCE_ENABLE
|
|
def_bool n
|
|
help
|
|
Select when the board requires that the power button is always
|
|
enabled.
|
|
|
|
config POWER_BUTTON_FORCE_DISABLE
|
|
def_bool n
|
|
help
|
|
Select when the board requires that the power button is always
|
|
disabled, e.g. when it has been hardwired to ground.
|
|
|
|
config POWER_BUTTON_IS_OPTIONAL
|
|
bool
|
|
default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
|
|
default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
|
|
help
|
|
Internal option that controls ENABLE_POWER_BUTTON visibility.
|
|
|
|
source src/Kconfig.deprecated_options
|