coreboot-kgpe-d16/src/mainboard/gigabyte
Arthur Heymans 0a4e0fd913 cpu/intel/speedstep: Fix the PNOT ACPI method
The PNOT method never notifies the CPU to update it's _CST methods due
to reliance on inexisting variable (PDCx).

Add a method in the speedstep ssdt generator to notify all available
CPU nodes and hook this up in this file.

The cpu.asl file is moved to cpu/intel/speedstep/acpi since it now
relies on code generated in the speedstep ssdt generator. CPUs not
using the speedstep code never included this PNOT method so this is
a logical place for this code to be.

Change-Id: Ie2ba5e07b401d6f7c80c31f2bfcd9ef3ac0c1ad1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-01-17 17:09:13 +00:00
..
ga-6bxc intel/i440bx: Move LATE_CBMEM_INIT under mainboard 2017-09-01 14:39:16 +00:00
ga-6bxe intel/i440bx: Move LATE_CBMEM_INIT under mainboard 2017-09-01 14:39:16 +00:00
ga-945gcm-s2l cpu/intel/speedstep: Fix the PNOT ACPI method 2018-01-17 17:09:13 +00:00
ga-b75m-d3h intel/bd82x6x: Use generated ACPI PIRQ 2017-12-20 16:48:23 +00:00
ga-b75m-d3v intel/bd82x6x: Use generated ACPI PIRQ 2017-12-20 16:48:23 +00:00
ga-g41m-es2l mb/*/*/romstage.c: Clean up targets with i82801gx 2018-01-14 21:43:25 +00:00
ga_2761gxdk mb/*/*: Remove rtc nvram configurable baud rate 2017-09-23 11:06:25 +00:00
m57sli mb/*/*: Remove rtc nvram configurable baud rate 2017-09-23 11:06:25 +00:00
ma78gm AMD fam10: Link southbridge/amd/rs780/early_setup.c 2017-12-11 11:58:02 +00:00
ma785gm AMD fam10: Link southbridge/amd/rs780/early_setup.c 2017-12-11 11:58:02 +00:00
ma785gmt AMD fam10: Link southbridge/amd/rs780/early_setup.c 2017-12-11 11:58:02 +00:00
Kconfig
Kconfig.name