c8feeddf34
We used several names for that same value, and hardcoded the value at some more places. They're all LOCAL_APIC_ADDR now (except for lapic specific code that still uses LAPIC_DEFAULT_BASE). Change-Id: I1d4be73b1984f22b7e84681edfadf0588a7589b6 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/676 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
109 lines
3.6 KiB
C
109 lines
3.6 KiB
C
#include <console/console.h>
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#include <arch/smp/mpspec.h>
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#include <arch/ioapic.h>
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#include <device/pci.h>
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#include <string.h>
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#include <stdint.h>
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#include <cpu/amd/amdk8_sysconf.h>
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extern unsigned char bus_8131_0;
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extern unsigned char bus_8131_1;
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extern unsigned char bus_8131_2;
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extern unsigned char bus_8111_0;
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extern unsigned char bus_8111_1;
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extern unsigned apicid_8111;
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extern unsigned apicid_8131_1;
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extern unsigned apicid_8131_2;
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extern unsigned sbdn3;
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static void *smp_write_config_table(void *v)
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{
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struct mp_config_table *mc;
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int i, bus_isa;
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mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
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mptable_init(mc, LOCAL_APIC_ADDR);
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smp_write_processors(mc);
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get_bus_conf();
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mptable_write_buses(mc, NULL, &bus_isa);
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/*I/O APICs: APIC ID Version State Address*/
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smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR);
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{
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device_t dev;
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struct resource *res;
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dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
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if (dev) {
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res = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (res) {
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smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
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}
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}
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dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
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if (dev) {
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res = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (res) {
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smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
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}
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}
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}
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mptable_add_isa_interrupts(mc, bus_isa, apicid_8111, 0);
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/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
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//8111 LPC ????
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ((sysconf.sbdn+1)<<2)|0, apicid_8111, 0x13);
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//On Board AMD USB ???
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13);
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//On Board ATI Display Adapter
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (6<<2)|0, apicid_8111, 0x12);
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//On Board SI Serial ATA
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (5<<2)|0, apicid_8111, 0x11);
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//Slot 3 PCIX 100/66
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for(i=0;i<4;i++) {
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|i, apicid_8131_1, (3+i)%4); //27
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}
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//On Board NIC and adaptec scsi
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for(i=0;i<2;i++) {
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|i, apicid_8131_1, (0+i)%4); //24
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|i, apicid_8131_1, (0+i)%4); //24
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}
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//Slot 1 PCI-X 133/100/66 or Side 1 on raiser card
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for(i=0;i<4;i++) {
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|i, apicid_8131_2, (0+i)%4); //28
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}
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//Slot 1 PCI-X 133/100/66, Side 2 on raiser card
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//Fix ME, IRQ Pins?
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for(i=0;i<4;i++) {
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|i, apicid_8131_2, (1+i)%4); //28
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}
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/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
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mptable_lintsrc(mc, bus_isa);
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/* There is no extension information... */
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/* Compute the checksums */
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return mptable_finalize(mc);
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}
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unsigned long write_smp_table(unsigned long addr)
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{
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void *v;
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v = smp_write_floating_table(addr, 0);
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return (unsigned long)smp_write_config_table(v);
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}
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