2efc8808b8
The code supports DDR3 boards only. RAM init for DDR2 is sufficiently different that it requires separate code, and we have no boards to test that. Change-Id: I9076546faf8a2033c89eb95f5eec524439ab9fe1 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1689 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
15 lines
650 B
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15 lines
650 B
Text
source src/northbridge/intel/e7501/Kconfig
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source src/northbridge/intel/e7505/Kconfig
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source src/northbridge/intel/e7520/Kconfig
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source src/northbridge/intel/e7525/Kconfig
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source src/northbridge/intel/i3100/Kconfig
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source src/northbridge/intel/i440bx/Kconfig
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source src/northbridge/intel/i440lx/Kconfig
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source src/northbridge/intel/i82810/Kconfig
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source src/northbridge/intel/i82830/Kconfig
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source src/northbridge/intel/i855/Kconfig
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source src/northbridge/intel/i945/Kconfig
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source src/northbridge/intel/gm45/Kconfig
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source src/northbridge/intel/sch/Kconfig
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source src/northbridge/intel/i5000/Kconfig
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source src/northbridge/intel/sandybridge/Kconfig
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