2efc8808b8
The code supports DDR3 boards only. RAM init for DDR2 is sufficiently different that it requires separate code, and we have no boards to test that. Change-Id: I9076546faf8a2033c89eb95f5eec524439ab9fe1 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/1689 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
16 lines
836 B
Makefile
16 lines
836 B
Makefile
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_E7501) += e7501
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_E7505) += e7505
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_E7520) += e7520
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_E7525) += e7525
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I3100) += i3100
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I440BX) += i440bx
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I440LX) += i440lx
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I82810) += i82810
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I82830) += i82830
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I855) += i855
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945) += i945
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_GM45) += gm45
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SCH) += sch
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I5000) += i5000
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += sandybridge
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subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += sandybridge
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