coreboot-kgpe-d16/src
Furquan Shaikh 0af1926353 drivers/wifi: Drop maxsleep parameter from chip config
This change drops maxsleep parameter from chip config and instead
hardcodes the deepest sleep state from which the WiFi device can wake
the system up from to SLP_TYP_S3. This is similar to how other device
drivers in coreboot report _PRW property in ACPI. It relieves the
users from adding another register attribute to devicetree since all
mainboards configure the same value. If this changes in the future, it
should be easy to bring the maxsleep config parameter back.

BUG=b:169802515
BRANCH=zork

Change-Id: I42131fced008da0d51f0f777b7f2d99deaf68827
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-11 02:14:21 +00:00
..
acpi acpi: Add SSDT pstate helper functions 2020-09-22 16:06:34 +00:00
arch cpu/qemu-x86/car: Move long mode entry right before c entry 2020-09-29 12:27:04 +00:00
commonlib src/commonlib: Drop unneeded empty lines 2020-09-21 15:53:25 +00:00
console src/console: Drop unneeded empty lines 2020-09-21 15:52:42 +00:00
cpu drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config 2020-10-02 23:11:04 +00:00
device pci_device: Add a helper function for determining if PCI device is wake source 2020-10-11 02:13:17 +00:00
drivers drivers/wifi: Drop maxsleep parameter from chip config 2020-10-11 02:14:21 +00:00
ec ec/hp/kbc1126: Support not putting EC firmware in CBFS 2020-09-28 09:26:54 +00:00
include pci_device: Add a helper function for determining if PCI device is wake source 2020-10-11 02:13:17 +00:00
lib trogdor: Modify DDR training to use mrc_cache 2020-10-09 19:45:40 +00:00
mainboard drivers/wifi: Drop maxsleep parameter from chip config 2020-10-11 02:14:21 +00:00
northbridge nb/intel/ironlake: Move register headers into a subfolder 2020-10-10 20:00:00 +00:00
security security/intel/txt: Print chipset as hex value 2020-10-08 15:38:19 +00:00
soc soc/intel/tigerlake: Add chipset devicetree 2020-10-09 23:26:04 +00:00
southbridge lynxpoint/broadwell: Relegate IOBP printk to BIOS_SPEW 2020-10-08 08:00:41 +00:00
superio superio/ite: Distinguish between chips for PECI readings 2020-09-22 01:11:02 +00:00
vendorcode vc/intel/fsp/fsp2_0/cpx_sp: Expose DIMM Present and DdrVoltage fields 2020-10-08 12:08:31 +00:00
Kconfig sconfig: Allow chipset to provide a base devicetree 2020-10-09 23:25:46 +00:00