Raul E Rangel 0b123dd72e soc/amd/cezanne/acpi: Add pci0.asl ... This differs slightly from picasso. The PCI BAR region is between TOM1 and CONFIG_MMCONF_BASE_ADDRESS. This matches what the Intel platforms are doing. It also matches what linux derives from the e820 tables: > [mem 0xd0000000-0xf7ffffff] available for PCI devices Picasso currently declares the region between TOM and IO_APIC_ADDR. This region includes MMCONF. We don't want to map any PCI BARs in this region. TEST=Boot majolica and check logs pci_bus 0000:00: root bus resource [io 0x0000-0x0cf7 window] pci_bus 0000:00: root bus resource [io 0x0d00-0xffff window] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff] pci_bus 0000:00: root bus resource [mem 0x000c0000-0x000dffff] pci_bus 0000:00: root bus resource [mem 0xd0000000-0xf7ffffff] pci_bus 0000:00: root bus resource [bus 00-3f] Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4ff02012795e2166e3a4197071b1136727089318 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50893 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2021-02-22 07:29:31 +00:00
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cezanne	soc/amd/cezanne/acpi: Add pci0.asl	2021-02-22 07:29:31 +00:00
common	soc/amd: Move root complex SSDT TOM1/TOM2 generation function	2021-02-22 07:29:19 +00:00
picasso	soc/amd: Move root complex SSDT TOM1/TOM2 generation function	2021-02-22 07:29:19 +00:00
stoneyridge	ACPI: Use common OperationRegion for PCI_MMCONF	2021-02-20 21:38:54 +00:00
Kconfig