6b5bc77c9b
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
89 lines
2.3 KiB
C
89 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ops.h>
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#include "i82801gx.h"
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#include "sata.h"
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static void ich_hide_devfn(unsigned int devfn)
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{
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switch (devfn) {
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case PCI_DEVFN(27, 0): /* HD Audio Controller */
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RCBA32_OR(FD, FD_HDAUD);
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break;
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case PCI_DEVFN(28, 0): /* PCI Express Root Port 1 */
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case PCI_DEVFN(28, 1): /* PCI Express Root Port 2 */
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case PCI_DEVFN(28, 2): /* PCI Express Root Port 3 */
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case PCI_DEVFN(28, 3): /* PCI Express Root Port 4 */
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case PCI_DEVFN(28, 4): /* PCI Express Root Port 5 */
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case PCI_DEVFN(28, 5): /* PCI Express Root Port 6 */
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RCBA32_OR(FD, ICH_DISABLE_PCIE(PCI_FUNC(devfn)));
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break;
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case PCI_DEVFN(29, 0): /* UHCI #1 */
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case PCI_DEVFN(29, 1): /* UHCI #2 */
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case PCI_DEVFN(29, 2): /* UHCI #3 */
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case PCI_DEVFN(29, 3): /* UHCI #4 */
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RCBA32_OR(FD, ICH_DISABLE_UHCI(PCI_FUNC(devfn)));
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break;
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case PCI_DEVFN(29, 7): /* EHCI #1 */
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RCBA32_OR(FD, FD_EHCI);
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break;
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case PCI_DEVFN(30, 2): /* AC Audio */
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RCBA32_OR(FD, FD_ACAUD);
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break;
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case PCI_DEVFN(30, 3): /* AC Modem */
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RCBA32_OR(FD, FD_ACMOD);
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break;
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case PCI_DEVFN(31, 0): /* LPC */
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RCBA32_OR(FD, FD_LPCB);
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break;
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case PCI_DEVFN(31, 1): /* PATA #1 */
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RCBA32_OR(FD, FD_PATA);
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break;
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case PCI_DEVFN(31, 2): /* SATA #1 */
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RCBA32_OR(FD, FD_SATA);
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break;
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case PCI_DEVFN(31, 3): /* SMBUS */
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RCBA32_OR(FD, FD_SMBUS);
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break;
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}
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}
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void i82801gx_enable(struct device *dev)
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{
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u16 reg16;
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if (!dev->enabled) {
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printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));
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/* Ensure memory, io, and bus master are all disabled */
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reg16 = pci_read_config16(dev, PCI_COMMAND);
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reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
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pci_write_config16(dev, PCI_COMMAND, reg16);
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/* Hide this device if possible */
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ich_hide_devfn(dev->path.pci.devfn);
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} else {
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/* Enable SERR */
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pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR);
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if (dev->path.pci.devfn == PCI_DEVFN(31, 2)) {
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printk(BIOS_DEBUG, "Set SATA mode early\n");
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sata_enable(dev);
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}
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}
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}
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static void i82801gx_init(void *chip_info)
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{
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/* Disable performance counter */
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RCBA32_OR(FD, 1);
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}
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struct chip_operations southbridge_intel_i82801gx_ops = {
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CHIP_NAME("Intel ICH7/ICH7-M (82801Gx) Series Southbridge")
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.enable_dev = i82801gx_enable,
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.init = i82801gx_init,
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};
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