b36100faf4
For consistency with other platforms, use `SOC_INTEL_GEMINILAKE`. Change-Id: I06310e5a9bca6c9504f19a6c2fe9b26626f290d4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
82 lines
2 KiB
C
82 lines
2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* The sole purpose of this driver is to avoid BAR to be changed during
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* resource allocation. Since configuration space is just 32 bytes it
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* shouldn't cause any fragmentation.
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*/
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#include <console/console.h>
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#include <intelblocks/uart.h>
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#include <soc/gpio.h>
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#include <soc/pci_devs.h>
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/* UART pad configuration. Support RXD and TXD for now. */
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const struct uart_gpio_pad_config uart_gpio_pads[] = {
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#if CONFIG(SOC_INTEL_GEMINILAKE)
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{
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.console_index = 0,
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.gpios = {
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PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_60, NATIVE, DEEP, NF1,
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HIZCRx1, DISPUPD), /* LPSS_UART0_RXD */
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PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_61, NATIVE, DEEP, NF1,
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HIZCRx1, DISPUPD), /* LPSS_UART0_TXD */
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},
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},
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{
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.console_index = 2,
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.gpios = {
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PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, NATIVE, DEEP, NF1,
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HIZCRx1, DISPUPD), /* LPSS_UART2_RXD */
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PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, NATIVE, DEEP, NF1,
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HIZCRx1, DISPUPD), /* LPSS_UART2_TXD */
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},
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},
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#else
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{
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.console_index = 0,
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.gpios = {
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PAD_CFG_NF(GPIO_38, NATIVE, DEEP, NF1), /* UART0 RX */
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PAD_CFG_NF(GPIO_39, NATIVE, DEEP, NF1), /* UART0 TX */
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},
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},
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{
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.console_index = 1,
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.gpios = {
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PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), /* UART1 RX */
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PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1), /* UART1 TX */
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},
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},
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{
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.console_index = 2,
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.gpios = {
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PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* UART2 RX */
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PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* UART2 TX */
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},
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},
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#endif
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};
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const int uart_max_index = ARRAY_SIZE(uart_gpio_pads);
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DEVTREE_CONST struct device *soc_uart_console_to_device(int uart_console)
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{
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/*
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* if index is valid, this function will return corresponding structure
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* for uart console else will return NULL.
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*/
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switch (uart_console) {
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case 0:
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return pcidev_path_on_root(PCH_DEVFN_UART0);
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case 1:
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return pcidev_path_on_root(PCH_DEVFN_UART1);
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case 2:
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return pcidev_path_on_root(PCH_DEVFN_UART2);
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case 3:
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return pcidev_path_on_root(PCH_DEVFN_UART3);
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default:
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printk(BIOS_ERR, "Invalid UART console index\n");
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return NULL;
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}
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}
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