05dfe3177d
Clone entirely from Jasperlake List of changes on top off initial jasperlake clone 1. Replace "Jasperlake" with "Elkhartlake" 2. Replace "jsl" with "ehl" 3. Replace "jsp" with "mcc" 4. Rename structure based on Jasperlake with Elkhartlake 5. Clean up upd override in fsp_params.c will be added later 6. Sort #include files alphabetically as per comment 7. Remove doc details from espi.c until it is ready 8. Remove pch_isclk & camera clocks related codes 9. Add new #define NMI_STS_CNT & NMI_EN as per comment Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I372b0bb5912e013445ed8df7c58d0a9ee9a7cf35 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
62 lines
1.7 KiB
C
62 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
|
|
|
|
#include <delay.h>
|
|
#include <device/device.h>
|
|
#include <device/pci.h>
|
|
#include <device/pci_ops.h>
|
|
#include <intelblocks/power_limit.h>
|
|
#include <intelblocks/systemagent.h>
|
|
#include <soc/iomap.h>
|
|
#include <soc/soc_chip.h>
|
|
#include <soc/systemagent.h>
|
|
|
|
/*
|
|
* SoC implementation
|
|
*
|
|
* Add all known fixed memory ranges for Host Controller/Memory
|
|
* controller.
|
|
*/
|
|
void soc_add_fixed_mmio_resources(struct device *dev, int *index)
|
|
{
|
|
static const struct sa_mmio_descriptor soc_fixed_resources[] = {
|
|
{ PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH,
|
|
"PCIEXBAR" },
|
|
{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
|
|
{ DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },
|
|
{ EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" },
|
|
{ REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" },
|
|
{ EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },
|
|
};
|
|
|
|
sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,
|
|
ARRAY_SIZE(soc_fixed_resources));
|
|
|
|
/* Add Vt-d resources if VT-d is enabled */
|
|
if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE))
|
|
return;
|
|
|
|
sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources,
|
|
ARRAY_SIZE(soc_vtd_resources));
|
|
}
|
|
|
|
/*
|
|
* SoC implementation
|
|
*
|
|
* Perform System Agent Initialization during Ramstage phase.
|
|
*/
|
|
void soc_systemagent_init(struct device *dev)
|
|
{
|
|
struct soc_power_limits_config *soc_config;
|
|
config_t *config;
|
|
|
|
/* Enable Power Aware Interrupt Routing */
|
|
enable_power_aware_intr();
|
|
|
|
/* Enable BIOS Reset CPL */
|
|
enable_bios_reset_cpl();
|
|
|
|
mdelay(1);
|
|
config = config_of_soc();
|
|
soc_config = &config->power_limits_config;
|
|
set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config);
|
|
}
|