c5b87c8f89
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5575 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
121 lines
3.7 KiB
C
121 lines
3.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <arch/smp/mpspec.h>
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#include <device/pci.h>
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#include <string.h>
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#include <stdint.h>
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static void *smp_write_config_table(void *v)
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{
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static const char sig[4] = "PCMP";
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static const char oem[8] = "COREBOOT";
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static const char productid[12] = "ASUS P2B-DS ";
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struct mp_config_table *mc;
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mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
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memset(mc, 0, sizeof(*mc));
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memcpy(mc->mpc_signature, sig, sizeof(sig));
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mc->mpc_length = sizeof(*mc); /* initially just the header */
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mc->mpc_spec = 0x04;
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mc->mpc_checksum = 0; /* not yet computed */
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memcpy(mc->mpc_oem, oem, sizeof(oem));
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memcpy(mc->mpc_productid, productid, sizeof(productid));
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mc->mpc_oemptr = 0;
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mc->mpc_oemsize = 0;
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mc->mpc_entry_count = 0; /* No entries yet... */
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mc->mpc_lapic = LAPIC_ADDR;
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mc->mpe_length = 0;
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mc->mpe_checksum = 0;
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mc->reserved = 0;
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smp_write_processors(mc);
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/* Bus: Bus ID Type */
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smp_write_bus(mc, 0, "PCI ");
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smp_write_bus(mc, 1, "ISA ");
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/* I/O APICs: APIC ID Version State Address */
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smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
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{
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device_t dev;
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struct resource *res;
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dev = dev_find_slot(1, PCI_DEVFN(0x1e, 0));
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if (dev) {
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res = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (res)
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smp_write_ioapic(mc, 3, 0x20, res->base);
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}
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dev = dev_find_slot(1, PCI_DEVFN(0x1c, 0));
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if (dev) {
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res = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (res)
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smp_write_ioapic(mc, 4, 0x20, res->base);
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}
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dev = dev_find_slot(4, PCI_DEVFN(0x1e, 0));
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if (dev) {
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res = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (res)
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smp_write_ioapic(mc, 5, 0x20, res->base);
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}
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dev = dev_find_slot(4, PCI_DEVFN(0x1c, 0));
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if (dev) {
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res = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (res)
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smp_write_ioapic(mc, 8, 0x20, res->base);
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}
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}
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mptable_add_isa_interrupts(mc, 0x1, 0x2, 0);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
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0x0, 0x13, 0x2, 0x13);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
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0x0, 0x18, 0x2, 0x13);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
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0x0, 0x30, 0x2, 0x10);
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/* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
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smp_write_intsrc(mc, mp_ExtINT,
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MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 0x1, 0x0,
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MP_APIC_ALL, 0x0);
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smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
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0x1, 0x0, MP_APIC_ALL, 0x1);
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/* There is no extension information... */
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/* Compute the checksums */
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mc->mpe_checksum =
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smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
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mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
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printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
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mc, smp_next_mpe_entry(mc));
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return smp_next_mpe_entry(mc);
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}
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unsigned long write_smp_table(unsigned long addr)
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{
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void *v;
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v = smp_write_floating_table(addr);
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return (unsigned long)smp_write_config_table(v);
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}
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