coreboot-kgpe-d16/src/soc
Lijian Zhao 0c8237aa0d soc/intel/cannonlake: Change default UART number to 2
Set default UART number to 2 if 32bit PCI got selected, the proper debug
print can be seen from serial port in case of switch between platforms,
especially when change to lpss uart from legacy uart or vise versa.

Change-Id: If2e0e8c8ac86e49a245f3d1d4722d40be9c01e25
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21544
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-11 17:26:07 +00:00
..
amd soc/amd/stoneyridge: Pass firmware dir location to amdfwtool 2017-10-05 18:17:36 +00:00
broadcom/cygnus mb/*/*: Remove rtc nvram configurable baud rate 2017-09-23 11:06:25 +00:00
dmp/vortex86ex soc/dmp/vortex86: Fix CMOS read and random RTC reset 2017-08-01 13:20:15 +00:00
imgtec/pistachio mb/*/*: Remove rtc nvram configurable baud rate 2017-09-23 11:06:25 +00:00
intel soc/intel/cannonlake: Change default UART number to 2 2017-10-11 17:26:07 +00:00
lowrisc/lowrisc
marvell/mvmap2315 Update files with no newline at the end 2017-07-24 15:08:16 +00:00
mediatek/mt8173 mb/*/*: Remove rtc nvram configurable baud rate 2017-09-23 11:06:25 +00:00
nvidia mb/*/*: Remove rtc nvram configurable baud rate 2017-09-23 11:06:25 +00:00
qualcomm mb/*/*: Remove rtc nvram configurable baud rate 2017-09-23 11:06:25 +00:00
rockchip include/device: Split i2c.h into three 2017-08-18 15:33:29 +00:00
samsung mb/*/*: Remove rtc nvram configurable baud rate 2017-09-23 11:06:25 +00:00
ucb/riscv