coreboot-kgpe-d16/src/vendorcode
Nick Vaccaro 577afe62c9 vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2511_04
The headers added are generated as per FSP v2511_04
Previous FSP version was v2471_02
Changes include:
- UPDs description update in FspsUpd.h and FspmUpd.h
- Adjust UPD Offset in FspmUpd.h
- Name change of UPDs in FspmUpd.h and FspsUpd.h
- Copyright year is updated in FspmUpd.h and FspsUpd.h
- Updated spd_upds and dq_upds structure variables in meminit.c
- Updated structure member of s_cfg->LpmStateEnableMask to PmcLpmS0ixSubStateEnableMask
  in fsp_params.c

BUG=b:213959910
BRANCH=None
TEST=Build and boot brya

Cq-Depend: chrome-internal:4448696, chrome-internal:4445910
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.corp-partner.google.com>
Change-Id: I39646c6812afbf622171361b8206daeacdaafac0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-01-13 18:04:13 +00:00
..
amd Cezanne FSP wrapper: Sync with PI 1.0.0.5 2021-11-30 15:50:11 +00:00
cavium
eltan src/vendorcode/eltan: Don't reference CONFIG_CBFS_SIZE 2021-07-28 08:19:30 +00:00
google chromeos: Add an elog for Chrome OS diagnostic boot 2022-01-11 23:44:51 +00:00
intel vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2511_04 2022-01-13 18:04:13 +00:00
mediatek vc/mediatek/mt8195: Fix rank1 CKE setting for single-rank DRAM 2021-12-01 09:48:17 +00:00
siemens
Makefile.inc