70d79a4546
Change-Id: I43b9b86fd51dbdc50108026099c60238f3012cbe Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16290 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker
116 lines
3.1 KiB
C
116 lines
3.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2013 Sage Electronic Engineering, LLC.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include "pch.h"
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typedef struct southbridge_intel_fsp_i89xx_config config_t;
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static void sata_init(struct device *dev)
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{
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u32 reg32;
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u16 reg16;
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/* Get the chip configuration */
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config_t *config = dev->chip_info;
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printk(BIOS_DEBUG, "SATA: Initializing...\n");
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if (config == NULL) {
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printk(BIOS_ERR, "SATA: ERROR: Device not in devicetree.cb!\n");
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return;
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}
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/* SATA configuration is handled by the FSP */
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/* Enable BARs */
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pci_write_config16(dev, PCI_COMMAND, 0x0007);
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if (config->ide_legacy_combined) {
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printk(BIOS_DEBUG, "SATA: Controller in combined mode.\n");
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/* No AHCI: clear AHCI base */
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pci_write_config32(dev, 0x24, 0x00000000);
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/* And without AHCI BAR no memory decoding */
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reg16 = pci_read_config16(dev, PCI_COMMAND);
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reg16 &= ~PCI_COMMAND_MEMORY;
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pci_write_config16(dev, PCI_COMMAND, reg16);
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} else if (config->sata_ahci) {
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u32 *abar;
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printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n");
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/* Set Interrupt Line */
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/* Interrupt Pin is set by D31IP.PIP */
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pci_write_config8(dev, INTR_LN, 0x0a);
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/* Initialize AHCI memory-mapped space */
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abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
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printk(BIOS_DEBUG, "ABAR: %p\n", abar);
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/* Enable AHCI Mode */
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reg32 = read32(abar + 0x04);
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reg32 |= (1 << 31);
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write32(abar + 0x04, reg32);
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} else {
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printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n");
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/* Set Interrupt Line */
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/* Interrupt Pin is set by D31IP.PIP */
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pci_write_config8(dev, INTR_LN, 0xff);
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}
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}
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static void sata_enable(device_t dev)
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{
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}
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static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)
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{
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if (!vendor || !device) {
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pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
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pci_read_config32(dev, PCI_VENDOR_ID));
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} else {
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pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
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((device & 0xffff) << 16) | (vendor & 0xffff));
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}
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}
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static struct pci_operations sata_pci_ops = {
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.set_subsystem = sata_set_subsystem,
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};
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static struct device_operations sata_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = sata_init,
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.enable = sata_enable,
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.scan_bus = 0,
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.ops_pci = &sata_pci_ops,
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};
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static const unsigned short pci_device_ids[] = { 0x2321, 0x2323, 0x2326, 0 };
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static const struct pci_driver pch_sata __pci_driver = {
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.ops = &sata_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.devices = pci_device_ids,
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};
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