a73b93157f
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
74 lines
2.2 KiB
C
74 lines
2.2 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Rockchip Inc.
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* Copyright 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <assert.h>
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#include <bootblock_common.h>
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#include <console/console.h>
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#include <delay.h>
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#include <reset.h>
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#include <soc/clock.h>
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#include <soc/i2c.h>
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#include <soc/grf.h>
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#include <soc/pmu.h>
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#include <soc/rk808.h>
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#include <soc/spi.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include "board.h"
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void bootblock_mainboard_early_init()
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{
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if (IS_ENABLED(CONFIG_DRIVERS_UART)) {
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assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE);
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write32(&rk3288_grf->iomux_uart2, IOMUX_UART2);
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}
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}
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void bootblock_mainboard_init(void)
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{
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if (rkclk_was_watchdog_reset())
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reboot_from_watchdog();
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/* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */
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setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
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setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
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assert(CONFIG_PMIC_BUS == 0); /* must correspond with IOMUX */
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i2c_init(CONFIG_PMIC_BUS, 400*KHz);
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/* Slowly raise to max CPU voltage to prevent overshoot */
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rk808_configure_buck(1, 1200);
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udelay(175);/* Must wait for voltage to stabilize,2mV/us */
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rk808_configure_buck(1, 1400);
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udelay(100);/* Must wait for voltage to stabilize,2mV/us */
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rkclk_configure_cpu(APLL_1800_MHZ);
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/* i2c1 for tpm */
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write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
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i2c_init(1, 400*KHz);
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/* spi2 for firmware ROM */
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write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
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write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
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rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
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/* spi0 for chrome ec */
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write32(&rk3288_grf->iomux_spi0, IOMUX_SPI0);
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rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 8250*KHz);
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setup_chromeos_gpios();
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}
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