0dbea48d46
I2C driver is replicated in each generation of AMD SoCs. Introduce a
common I2C driver that can be used across all the AMD SoCs. To begin
with, peripheral reset functionality is moved into this common driver.
SoC specific I2C driver passes the SCL pin configuration in order for
the common driver to reset the peripherals. More functionality can be
moved here in subsequent changes.
Also sb_reset_i2c_slaves() is renamed as sb_reset_i2c_peripherals() as
an effort towards using inclusive language.
BUG=None
TEST=Build Dalboz and Grunt. Boot to OS in Dalboz. Ensure that the I2C
peripherals are detected as earlier in Dalboz.
localhost ~ # i2cdetect -y 0
Warning: Can't use SMBus Quick Write command, will skip some addresses
0 1 2 3 4 5 6 7 8 9 a b c d e f
00:
10:
20:
30: -- -- -- -- -- -- -- --
40:
50: 50 51 -- -- -- -- -- -- 58 59 -- -- -- -- -- --
60:
70:
localhost ~ # i2cdetect -y 1
Warning: Can't use SMBus Quick Write command, will skip some addresses
0 1 2 3 4 5 6 7 8 9 a b c d e f
00:
10:
20:
30: -- -- -- -- -- -- -- --
40:
50: UU -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
60:
70:
Change-Id: I9f735dcfe8375abdc88ff06e8c4f8a6b741bc085
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Suggested-by: Kyosti Malkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
505 lines
13 KiB
Text
505 lines
13 KiB
Text
# SPDX-License-Identifier: GPL-2.0-only
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config SOC_AMD_PICASSO
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bool
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help
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AMD Picasso support
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if SOC_AMD_PICASSO
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config CPU_SPECIFIC_OPTIONS
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def_bool y
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select ARCH_BOOTBLOCK_X86_32
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select ARCH_VERSTAGE_X86_32 if !VBOOT_STARTS_BEFORE_BOOTBLOCK
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select ARCH_ROMSTAGE_X86_32
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select ARCH_RAMSTAGE_X86_32
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select RESET_VECTOR_IN_RAM
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select X86_AMD_FIXED_MTRRS
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select X86_AMD_INIT_SIPI
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select ACPI_SOC_NVS
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select DRIVERS_I2C_DESIGNWARE
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select DRIVERS_USB_PCI_XHCI
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select GENERIC_GPIO_LIB
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select IDT_IN_EVERY_STAGE
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select IOAPIC
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select HAVE_ACPI_TABLES
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select HAVE_EM100_SUPPORT
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select SOC_AMD_COMMON
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select SOC_AMD_COMMON_BLOCK_ACPI
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select SOC_AMD_COMMON_BLOCK_ACPIMMIO
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select SOC_AMD_COMMON_BLOCK_AOAC
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select SOC_AMD_COMMON_BLOCK_APOB
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select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
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select SOC_AMD_COMMON_BLOCK_DATA_FABRIC
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select SOC_AMD_COMMON_BLOCK_GRAPHICS
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select SOC_AMD_COMMON_BLOCK_HAS_ESPI
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select SOC_AMD_COMMON_BLOCK_HDA
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select SOC_AMD_COMMON_BLOCK_I2C
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select SOC_AMD_COMMON_BLOCK_IOMMU
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select SOC_AMD_COMMON_BLOCK_LPC
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select SOC_AMD_COMMON_BLOCK_NONCAR
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select SOC_AMD_COMMON_BLOCK_PCI
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select SOC_AMD_COMMON_BLOCK_PSP_GEN2
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select SOC_AMD_COMMON_BLOCK_SATA
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select SOC_AMD_COMMON_BLOCK_SMBUS
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select SOC_AMD_COMMON_BLOCK_SMI
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select SOC_AMD_COMMON_BLOCK_SMM
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select SOC_AMD_COMMON_BLOCK_SMU
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select SOC_AMD_COMMON_BLOCK_SPI
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select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H
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select SOC_AMD_COMMON_BLOCK_UART
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select SOC_AMD_COMMON_BLOCK_UCODE
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select PROVIDES_ROM_SHARING
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select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
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select PARALLEL_MP
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select PARALLEL_MP_AP_WORK
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select HAVE_SMI_HANDLER
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select SSE2
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select RTC
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select PLATFORM_USES_FSP2_0
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select FSP_COMPRESS_FSP_M_LZMA
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select FSP_COMPRESS_FSP_S_LZMA
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select UDK_2017_BINDING
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select HAVE_CF9_RESET
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config SOC_AMD_COMMON_BLOCK_UCODE_SIZE
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default 3200
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config FSP_M_FILE
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string "FSP-M (memory init) binary path and filename"
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depends on ADD_FSP_BINARIES
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default "3rdparty/amd_blobs/picasso/PICASSO_M.fd"
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help
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The path and filename of the FSP-M binary for this platform.
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config FSP_S_FILE
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string "FSP-S (silicon init) binary path and filename"
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depends on ADD_FSP_BINARIES
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default "3rdparty/amd_blobs/picasso/PICASSO_S.fd"
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help
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The path and filename of the FSP-S binary for this platform.
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config EARLY_RESERVED_DRAM_BASE
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hex
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default 0x2000000
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help
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This variable defines the base address of the DRAM which is reserved
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for usage by coreboot in early stages (i.e. before ramstage is up).
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This memory gets reserved in BIOS tables to ensure that the OS does
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not use it, thus preventing corruption of OS memory in case of S3
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resume.
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config EARLYRAM_BSP_STACK_SIZE
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hex
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default 0x1000
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config PSP_APOB_DRAM_ADDRESS
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hex
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default 0x2001000
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help
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Location in DRAM where the PSP will copy the AGESA PSP Output
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Block.
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config PSP_SHAREDMEM_BASE
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hex
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default 0x2011000 if VBOOT
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default 0x0
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help
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This variable defines the base address in DRAM memory where PSP copies
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vboot workbuf to. This is used in linker script to have a static
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allocation for the buffer as well as for adding relevant entries in
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BIOS directory table for the PSP.
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config PSP_SHAREDMEM_SIZE
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hex
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default 0x8000 if VBOOT
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default 0x0
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help
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Sets the maximum size for the PSP to pass the vboot workbuf and
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any logs or timestamps back to coreboot. This will be copied
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into main memory by the PSP and will be available when the x86 is
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started. The workbuf's base depends on the address of the reset
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vector.
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config PRERAM_CBMEM_CONSOLE_SIZE
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hex
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default 0x1600
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help
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Increase this value if preram cbmem console is getting truncated
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config C_ENV_BOOTBLOCK_SIZE
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hex
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default 0x10000
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help
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Sets the size of the bootblock stage that should be loaded in DRAM.
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This variable controls the DRAM allocation size in linker script
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for bootblock stage.
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config ROMSTAGE_ADDR
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hex
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default 0x2040000
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help
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Sets the address in DRAM where romstage should be loaded.
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config ROMSTAGE_SIZE
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hex
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default 0x80000
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help
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Sets the size of DRAM allocation for romstage in linker script.
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config FSP_M_ADDR
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hex
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default 0x20C0000
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help
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Sets the address in DRAM where FSP-M should be loaded. cbfstool
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performs relocation of FSP-M to this address.
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config FSP_M_SIZE
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hex
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default 0x80000
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help
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Sets the size of DRAM allocation for FSP-M in linker script.
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config VERSTAGE_ADDR
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hex
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depends on VBOOT_SEPARATE_VERSTAGE
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default 0x2140000
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help
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Sets the address in DRAM where verstage should be loaded if running
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as a separate stage on x86.
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config VERSTAGE_SIZE
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hex
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depends on VBOOT_SEPARATE_VERSTAGE
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default 0x80000
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help
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Sets the size of DRAM allocation for verstage in linker script if
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running as a separate stage on x86.
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config RAMBASE
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hex
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default 0x10000000
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config CPU_ADDR_BITS
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int
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default 48
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config MMCONF_BASE_ADDRESS
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default 0xF8000000
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config MMCONF_BUS_NUMBER
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default 64
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config VERSTAGE_ADDR
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hex
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default 0x4000000
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config MAX_CPUS
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int
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default 8
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config VGA_BIOS_ID
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string
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default "1002,15d8,c1"
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help
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The default VGA BIOS PCI vendor/device ID should be set to the
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result of the map_oprom_vendev_rev() function in northbridge.c.
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config VGA_BIOS_FILE
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string
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default "3rdparty/amd_blobs/picasso/PicassoGenericVbios.bin"
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config VGA_BIOS_SECOND
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def_bool y
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config VGA_BIOS_SECOND_ID
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string
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default "1002,15dd,c4"
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help
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Because Dali and Picasso need different video BIOSes, but have the
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same vendor/device IDs, we need an alternate method to determine the
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correct video BIOS. In map_oprom_vendev_rev(), we look at the cpuid
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and decide which rom to load.
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Even though the hardware has the same vendor/device IDs, the vBIOS
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contains a *different* device ID, confusing the situation even more.
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config VGA_BIOS_SECOND_FILE
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string
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default "3rdparty/amd_blobs/picasso/Raven2GenericVbios.bin"
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config CHECK_REV_IN_OPROM_NAME
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bool
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default y
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help
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Select this in the platform BIOS or chipset if the option rom has a
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revision that needs to be checked when searching CBFS.
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config S3_VGA_ROM_RUN
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bool
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default n
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config HEAP_SIZE
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hex
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default 0xc0000
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config SERIRQ_CONTINUOUS_MODE
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bool
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default n
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help
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Set this option to y for serial IRQ in continuous mode.
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Otherwise it is in quiet mode.
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config CONSOLE_UART_BASE_ADDRESS
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depends on CONSOLE_SERIAL && AMD_SOC_CONSOLE_UART
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hex
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default 0xfedc9000 if UART_FOR_CONSOLE = 0
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default 0xfedca000 if UART_FOR_CONSOLE = 1
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default 0xfedc3000 if UART_FOR_CONSOLE = 2
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default 0xfedcf000 if UART_FOR_CONSOLE = 3
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config SMM_TSEG_SIZE
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hex
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default 0x800000 if HAVE_SMI_HANDLER
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default 0x0
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config SMM_RESERVED_SIZE
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hex
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default 0x180000
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config SMM_MODULE_STACK_SIZE
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hex
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default 0x800
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config ACPI_CPU_STRING
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string
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default "\\_SB.C%03d"
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config ACPI_BERT
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bool "Build ACPI BERT Table"
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default y
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depends on HAVE_ACPI_TABLES
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help
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Report Machine Check errors identified in POST to the OS in an
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ACPI Boot Error Record Table.
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config ACPI_BERT_SIZE
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hex
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default 0x4000 if ACPI_BERT
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default 0x0
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help
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Specify the amount of DRAM reserved for gathering the data used to
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generate the ACPI table.
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config ACPI_SSDT_PSD_INDEPENDENT
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bool "Allow core p-state independent transitions"
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default y
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help
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AMD recommends the ACPI _PSD object to be configured to cause
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cores to transition between p-states independently. A vendor may
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choose to generate _PSD object to allow cores to transition together.
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config CHROMEOS
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select ALWAYS_LOAD_OPROM
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select ALWAYS_RUN_OPROM
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config RO_REGION_ONLY
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string
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depends on CHROMEOS
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default "apu/amdfw"
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config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
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int
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default 150
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config DISABLE_SPI_FLASH_ROM_SHARING
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def_bool n
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help
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Instruct the chipset to not honor the EGPIO67_SPI_ROM_REQ pin
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which indicates a board level ROM transaction request. This
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removes arbitration with board and assumes the chipset controls
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the SPI flash bus entirely.
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config MAINBOARD_POWER_RESTORE
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def_bool n
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help
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This option determines what state to go to once power is restored
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after having been lost in S0. Select this option to automatically
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return to S0. Otherwise the system will remain in S5 once power
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is restored.
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config FSP_TEMP_RAM_SIZE
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hex
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default 0x40000
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help
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The amount of coreboot-allocated heap and stack usage by the FSP.
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menu "PSP Configuration Options"
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config AMD_FWM_POSITION_INDEX
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int "Firmware Directory Table location (0 to 5)"
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range 0 5
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default 0 if BOARD_ROMSIZE_KB_512
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default 1 if BOARD_ROMSIZE_KB_1024
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default 2 if BOARD_ROMSIZE_KB_2048
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default 3 if BOARD_ROMSIZE_KB_4096
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default 4 if BOARD_ROMSIZE_KB_8192
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default 5 if BOARD_ROMSIZE_KB_16384
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help
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Typically this is calculated by the ROM size, but there may
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be situations where you want to put the firmware directory
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table in a different location.
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0: 512 KB - 0xFFFA0000
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1: 1 MB - 0xFFF20000
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2: 2 MB - 0xFFE20000
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3: 4 MB - 0xFFC20000
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4: 8 MB - 0xFF820000
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5: 16 MB - 0xFF020000
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comment "AMD Firmware Directory Table set to location for 512KB ROM"
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depends on AMD_FWM_POSITION_INDEX = 0
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comment "AMD Firmware Directory Table set to location for 1MB ROM"
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depends on AMD_FWM_POSITION_INDEX = 1
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comment "AMD Firmware Directory Table set to location for 2MB ROM"
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depends on AMD_FWM_POSITION_INDEX = 2
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comment "AMD Firmware Directory Table set to location for 4MB ROM"
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depends on AMD_FWM_POSITION_INDEX = 3
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comment "AMD Firmware Directory Table set to location for 8MB ROM"
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depends on AMD_FWM_POSITION_INDEX = 4
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comment "AMD Firmware Directory Table set to location for 16MB ROM"
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depends on AMD_FWM_POSITION_INDEX = 5
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config AMDFW_CONFIG_FILE
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string
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default "src/soc/amd/picasso/fw.cfg"
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config PSP_LOAD_MP2_FW
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bool
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default n
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help
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Include the MP2 firmwares and configuration into the PSP build.
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If unsure, answer 'n'
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config PSP_LOAD_S0I3_FW
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bool
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default n
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help
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Select this item to include the S0i3 file into the PSP build.
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config HAVE_PSP_WHITELIST_FILE
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bool "Include a debug whitelist file in PSP build"
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default n
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help
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Support secured unlock prior to reset using a whitelisted
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number? This feature requires a signed whitelist image and
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bootloader from AMD.
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If unsure, answer 'n'
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config PSP_WHITELIST_FILE
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string "Debug whitelist file path"
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depends on HAVE_PSP_WHITELIST_FILE
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default "3rdparty/amd_blobs/picasso/PSP/wtl-rvn.sbin"
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config PSP_SHAREDMEM_SIZE
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hex "Maximum size of shared memory area"
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default 0x3000 if VBOOT
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default 0x0
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help
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Sets the maximum size for the PSP to pass the vboot workbuf and
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any logs or timestamps back to coreboot. This will be copied
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into main memory by the PSP and will be available when the x86 is
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started.
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config PSP_UNLOCK_SECURE_DEBUG
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bool "Unlock secure debug"
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default n
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help
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Select this item to enable secure debug options in PSP.
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config PSP_VERSTAGE_FILE
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string "Specify the PSP_verstage file path"
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depends on VBOOT_STARTS_BEFORE_BOOTBLOCK
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default "$(obj)/psp_verstage.bin"
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help
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Add psp_verstage file to the build & PSP Directory Table
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config PSP_VERSTAGE_SIGNING_TOKEN
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string "Specify the PSP_verstage Signature Token file path"
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depends on VBOOT_STARTS_BEFORE_BOOTBLOCK
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default ""
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help
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Add psp_verstage signature token to the build & PSP Directory Table
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endmenu
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config VBOOT
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select VBOOT_VBNV_CMOS
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select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
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config VBOOT_STARTS_BEFORE_BOOTBLOCK
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def_bool n
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depends on VBOOT
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select ARCH_VERSTAGE_ARMV7
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help
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Runs verstage on the PSP. Only available on
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certain Chrome OS branded parts from AMD.
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config VBOOT_HASH_BLOCK_SIZE
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hex
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default 0x9000
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depends on VBOOT_STARTS_BEFORE_BOOTBLOCK
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help
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Because the bulk of the time in psp_verstage to hash the RO cbfs is
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spent in the overhead of doing svc calls, increasing the hash block
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size significantly cuts the verstage hashing time as seen below.
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4k takes 180ms
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16k takes 44ms
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32k takes 33.7ms
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36k takes 32.5ms
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There's actually still room for an even bigger stack, but we've
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reached a point of diminishing returns.
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config CMOS_RECOVERY_BYTE
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hex
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default 0x51
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depends on VBOOT_STARTS_BEFORE_BOOTBLOCK
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help
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If the workbuf is not passed from the PSP to coreboot, set the
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recovery flag and reboot. The PSP will read this byte, mark the
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recovery request in VBNV, and reset the system into recovery mode.
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This is the byte before the default first byte used by VBNV
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(0x26 + 0x0E - 1)
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if VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK
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config RWA_REGION_ONLY
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string
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default "apu/amdfw_a"
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help
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Add a space-delimited list of filenames that should only be in the
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RW-A section.
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config RWB_REGION_ONLY
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string
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default "apu/amdfw_b"
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help
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Add a space-delimited list of filenames that should only be in the
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RW-B section.
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config PICASSO_FW_A_POSITION
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hex
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help
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Location of the AMD firmware in the RW_A region
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config PICASSO_FW_B_POSITION
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hex
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help
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Location of the AMD firmware in the RW_B region
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endif # VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK
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endif # SOC_AMD_PICASSO
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