ed6996f2ba
Change-Id: I3d14a40b4ed0dcc216dcac883e33749b7808f00d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
687 lines
17 KiB
C
687 lines
17 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pciexp.h>
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#include <device/pci_def.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <soc/gpio.h>
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#include <soc/lpc.h>
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#include <soc/iobp.h>
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#include <soc/pch.h>
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#include <soc/pci_devs.h>
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#include <soc/rcba.h>
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#include <soc/intel/broadwell/chip.h>
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#include <soc/cpu.h>
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#include <delay.h>
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/* Low Power variant has 6 root ports. */
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#define NUM_ROOT_PORTS 6
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struct root_port_config {
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/* RPFN is a write-once register so keep a copy until it is written */
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u32 orig_rpfn;
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u32 new_rpfn;
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u32 pin_ownership;
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u32 strpfusecfg1;
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u32 strpfusecfg2;
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u32 strpfusecfg3;
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u32 b0d28f0_32c;
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u32 b0d28f4_32c;
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u32 b0d28f5_32c;
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int coalesce;
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int gbe_port;
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int num_ports;
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struct device *ports[NUM_ROOT_PORTS];
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};
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static struct root_port_config rpc;
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static inline int root_port_is_first(struct device *dev)
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{
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return PCI_FUNC(dev->path.pci.devfn) == 0;
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}
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static inline int root_port_is_last(struct device *dev)
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{
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return PCI_FUNC(dev->path.pci.devfn) == (rpc.num_ports - 1);
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}
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/* Root ports are numbered 1..N in the documentation. */
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static inline int root_port_number(struct device *dev)
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{
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return PCI_FUNC(dev->path.pci.devfn) + 1;
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}
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static void root_port_config_update_gbe_port(void)
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{
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/* Is the Gbe Port enabled? */
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if (!((rpc.strpfusecfg1 >> 19) & 1))
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return;
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switch ((rpc.strpfusecfg1 >> 16) & 0x7) {
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case 0:
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rpc.gbe_port = 3;
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break;
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case 1:
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rpc.gbe_port = 4;
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break;
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case 2:
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case 3:
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case 4:
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case 5:
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/* Lanes 0-4 of Root Port 5. */
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rpc.gbe_port = 5;
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break;
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default:
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printk(BIOS_DEBUG, "Invalid GbE Port Selection.\n");
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}
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}
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static void pcie_iosf_port_grant_count(struct device *dev)
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{
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u8 update_val;
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u32 rpcd = (pci_read_config32(dev, 0xfc) >> 14) & 0x3;
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switch (rpcd) {
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case 1:
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case 3:
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update_val = 0x02;
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break;
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case 2:
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update_val = 0x22;
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break;
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default:
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update_val = 0x00;
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break;
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}
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RCBA32(0x103C) = (RCBA32(0x103C) & (~0xff)) | update_val;
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}
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static void root_port_init_config(struct device *dev)
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{
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int rp;
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u32 data = 0;
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u8 resp, id;
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if (root_port_is_first(dev)) {
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rpc.orig_rpfn = RCBA32(RPFN);
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rpc.new_rpfn = rpc.orig_rpfn;
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rpc.num_ports = NUM_ROOT_PORTS;
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rpc.gbe_port = -1;
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/* RP0 f5[3:0] = 0101b*/
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pci_update_config8(dev, 0xf5, ~0xa, 0x5);
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pcie_iosf_port_grant_count(dev);
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rpc.pin_ownership = pci_read_config32(dev, 0x410);
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root_port_config_update_gbe_port();
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pci_update_config8(dev, 0xe2, ~(3 << 4), (3 << 4));
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if (dev->chip_info != NULL) {
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config_t *config = dev->chip_info;
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rpc.coalesce = config->pcie_port_coalesce;
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}
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}
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rp = root_port_number(dev);
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if (rp > rpc.num_ports) {
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printk(BIOS_ERR, "Found Root Port %d, expecting %d\n",
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rp, rpc.num_ports);
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return;
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}
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/* Read the fuse configuration and pin ownership. */
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switch (rp) {
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case 1:
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rpc.strpfusecfg1 = pci_read_config32(dev, 0xfc);
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rpc.b0d28f0_32c = pci_read_config32(dev, 0x32c);
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break;
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case 5:
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rpc.strpfusecfg2 = pci_read_config32(dev, 0xfc);
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rpc.b0d28f4_32c = pci_read_config32(dev, 0x32c);
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break;
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case 6:
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rpc.b0d28f5_32c = pci_read_config32(dev, 0x32c);
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rpc.strpfusecfg3 = pci_read_config32(dev, 0xfc);
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break;
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default:
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break;
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}
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pci_update_config32(dev, 0x418, 0, 0x02000430);
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if (root_port_is_first(dev)) {
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/*
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* set RP0 PCICFG E2h[5:4] = 11b and E1h[6] = 1
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* before configuring ASPM
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*/
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id = 0xe0 + (u8)(RCBA32(RPFN) & 0x07);
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pch_iobp_exec(0xE00000E0, IOBP_PCICFG_READ, id, &data, &resp);
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data |= ((0x30 << 16) | (0x40 << 8));
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pch_iobp_exec(0xE00000E0, IOBP_PCICFG_WRITE, id, &data, &resp);
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}
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/* Cache pci device. */
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rpc.ports[rp - 1] = dev;
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}
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/* Update devicetree with new Root Port function number assignment */
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static void pch_pcie_device_set_func(int index, int pci_func)
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{
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struct device *dev;
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unsigned int new_devfn;
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dev = rpc.ports[index];
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/* Set the new PCI function field for this Root Port. */
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rpc.new_rpfn &= ~RPFN_FNMASK(index);
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rpc.new_rpfn |= RPFN_FNSET(index, pci_func);
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/* Determine the new devfn for this port */
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new_devfn = PCI_DEVFN(PCH_DEV_SLOT_PCIE, pci_func);
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if (dev->path.pci.devfn != new_devfn) {
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printk(BIOS_DEBUG,
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"PCH: PCIe map %02x.%1x -> %02x.%1x\n",
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PCI_SLOT(dev->path.pci.devfn),
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PCI_FUNC(dev->path.pci.devfn),
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PCI_SLOT(new_devfn), PCI_FUNC(new_devfn));
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dev->path.pci.devfn = new_devfn;
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}
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}
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static void pcie_enable_clock_gating(void)
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{
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int i;
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int enabled_ports = 0;
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int is_broadwell = !!(cpu_family_model() == BROADWELL_FAMILY_ULT);
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for (i = 0; i < rpc.num_ports; i++) {
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struct device *dev;
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int rp;
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dev = rpc.ports[i];
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rp = root_port_number(dev);
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if (!dev->enabled) {
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/* Configure shared resource clock gating. */
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if (rp == 1 || rp == 5 || rp == 6)
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pci_update_config8(dev, 0xe1, 0xc3, 0x3c);
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pci_update_config8(dev, 0xe2, ~(3 << 4), (3 << 4));
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pci_update_config32(dev, 0x420, ~(1 << 31), (1 << 31));
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/* Per-Port CLKREQ# handling. */
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if (gpio_is_native(18 + rp - 1))
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pci_update_config32(dev, 0x420, ~0, (3 << 29));
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/* Enable static clock gating. */
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if (rp == 1 && !rpc.ports[1]->enabled &&
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!rpc.ports[2]->enabled && !rpc.ports[3]->enabled) {
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pci_update_config8(dev, 0xe2, ~1, 1);
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pci_update_config8(dev, 0xe1, 0x7f, 0x80);
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} else if (rp == 5 || rp == 6) {
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pci_update_config8(dev, 0xe2, ~1, 1);
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pci_update_config8(dev, 0xe1, 0x7f, 0x80);
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}
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continue;
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}
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enabled_ports++;
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/* Enable dynamic clock gating. */
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pci_update_config8(dev, 0xe1, 0xfc, 0x03);
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pci_update_config8(dev, 0xe2, ~(1 << 6), (1 << 6));
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pci_update_config8(dev, 0xe8, ~(3 << 2), (2 << 2));
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/* Update PECR1 register. */
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pci_update_config8(dev, 0xe8, ~0, 3);
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if (is_broadwell) {
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pci_update_config32(dev, 0x324, ~((1 << 5) | (1 << 14)),
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((1 << 5) | (1 << 14)));
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} else {
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pci_update_config32(dev, 0x324, ~(1 << 5), (1 << 5));
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}
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/* Per-Port CLKREQ# handling. */
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if (gpio_is_native(18 + rp - 1))
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/*
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* In addition to D28Fx PCICFG 420h[30:29] = 11b,
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* set 420h[17] = 0b and 420[0] = 1b for L1 SubState.
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*/
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pci_update_config32(dev, 0x420, ~0x20000,
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(3 << 29) | 1);
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/* Configure shared resource clock gating. */
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if (rp == 1 || rp == 5 || rp == 6)
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pci_update_config8(dev, 0xe1, 0xc3, 0x3c);
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/* CLKREQ# VR Idle Enable */
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RCBA32_OR(0x2b1c, (1 << (16 + i)));
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}
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if (!enabled_ports)
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pci_update_config8(rpc.ports[0], 0xe1, ~(1 << 6), (1 << 6));
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}
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static void root_port_commit_config(void)
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{
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int i;
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/* If the first root port is disabled the coalesce ports. */
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if (!rpc.ports[0]->enabled)
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rpc.coalesce = 1;
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/* Perform clock gating configuration. */
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pcie_enable_clock_gating();
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for (i = 0; i < rpc.num_ports; i++) {
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struct device *dev;
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u32 reg32;
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int n = 0;
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dev = rpc.ports[i];
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if (dev == NULL) {
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printk(BIOS_ERR, "Root Port %d device is NULL?\n", i+1);
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continue;
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}
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if (dev->enabled)
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continue;
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printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));
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/* 8.2 Configuration of PCI Express Root Ports */
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pci_update_config32(dev, 0x338, ~(1 << 26), 1 << 26);
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do {
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reg32 = pci_read_config32(dev, 0x328);
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n++;
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if (((reg32 & 0xff000000) == 0x01000000) || (n > 50))
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break;
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udelay(100);
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} while (1);
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if (n > 50)
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printk(BIOS_DEBUG, "%s: Timeout waiting for 328h\n",
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dev_path(dev));
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pci_update_config32(dev, 0x408, ~(1 << 27), 1 << 27);
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/* Disable this device if possible */
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pch_disable_devfn(dev);
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}
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if (rpc.coalesce) {
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int current_func;
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/* For all Root Ports N enabled ports get assigned the lower
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* PCI function number. The disabled ones get upper PCI
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* function numbers. */
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current_func = 0;
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for (i = 0; i < rpc.num_ports; i++) {
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if (!rpc.ports[i]->enabled)
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continue;
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pch_pcie_device_set_func(i, current_func);
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current_func++;
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}
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/* Allocate the disabled devices' PCI function number. */
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for (i = 0; i < rpc.num_ports; i++) {
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if (rpc.ports[i]->enabled)
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continue;
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pch_pcie_device_set_func(i, current_func);
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current_func++;
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}
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}
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printk(BIOS_SPEW, "PCH: RPFN 0x%08x -> 0x%08x\n",
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rpc.orig_rpfn, rpc.new_rpfn);
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RCBA32(RPFN) = rpc.new_rpfn;
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}
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static void root_port_mark_disable(struct device *dev)
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{
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/* Mark device as disabled. */
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dev->enabled = 0;
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/* Mark device to be hidden. */
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rpc.new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn));
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}
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static void root_port_check_disable(struct device *dev)
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{
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int rp;
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/* Device already disabled. */
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if (!dev->enabled) {
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root_port_mark_disable(dev);
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return;
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}
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rp = root_port_number(dev);
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/* Is the GbE port mapped to this Root Port? */
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if (rp == rpc.gbe_port) {
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root_port_mark_disable(dev);
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return;
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}
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/* Check Root Port Configuration. */
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switch (rp) {
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case 2:
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/* Root Port 2 is disabled for all lane configurations
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* but config 00b (4x1 links). */
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if ((rpc.strpfusecfg1 >> 14) & 0x3) {
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root_port_mark_disable(dev);
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return;
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}
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break;
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case 3:
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/* Root Port 3 is disabled in config 11b (1x4 links). */
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if (((rpc.strpfusecfg1 >> 14) & 0x3) == 0x3) {
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root_port_mark_disable(dev);
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return;
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}
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break;
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case 4:
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/* Root Port 4 is disabled in configs 11b (1x4 links)
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* and 10b (2x2 links). */
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if ((rpc.strpfusecfg1 >> 14) & 0x2) {
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root_port_mark_disable(dev);
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return;
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}
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break;
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}
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/* Check Pin Ownership. */
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switch (rp) {
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case 1:
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/* Bit 0 is Root Port 1 ownership. */
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if ((rpc.pin_ownership & 0x1) == 0) {
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root_port_mark_disable(dev);
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return;
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}
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break;
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case 2:
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/* Bit 2 is Root Port 2 ownership. */
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if ((rpc.pin_ownership & 0x4) == 0) {
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root_port_mark_disable(dev);
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return;
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}
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break;
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case 6:
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/* Bits 7:4 are Root Port 6 pin-lane ownership. */
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if ((rpc.pin_ownership & 0xf0) == 0) {
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root_port_mark_disable(dev);
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return;
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}
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break;
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}
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}
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static void pcie_add_0x0202000_iobp(u32 reg)
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{
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u32 reg32;
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reg32 = pch_iobp_read(reg);
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reg32 += (0x2 << 16) | (0x2 << 8);
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pch_iobp_write(reg, reg32);
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}
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static void pch_pcie_early(struct device *dev)
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{
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config_t *config = dev->chip_info;
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int do_aspm = 0;
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int rp = root_port_number(dev);
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switch (rp) {
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case 1:
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case 2:
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case 3:
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case 4:
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/*
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* Bits 31:28 of b0d28f0 0x32c register correspond to
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* Root Ports 4:1.
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*/
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do_aspm = !!(rpc.b0d28f0_32c & (1 << (28 + rp - 1)));
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break;
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case 5:
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/*
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* Bit 28 of b0d28f4 0x32c register correspond to
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* Root Ports 4:1.
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*/
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do_aspm = !!(rpc.b0d28f4_32c & (1 << 28));
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break;
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case 6:
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/*
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* Bit 28 of b0d28f5 0x32c register correspond to
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* Root Ports 4:1.
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*/
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do_aspm = !!(rpc.b0d28f5_32c & (1 << 28));
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break;
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}
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/* Allow ASPM to be forced on in devicetree */
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if (config && (config->pcie_port_force_aspm & (1 << (rp - 1))))
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do_aspm = 1;
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printk(BIOS_DEBUG, "PCIe Root Port %d ASPM is %sabled\n",
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rp, do_aspm ? "en" : "dis");
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if (do_aspm) {
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/* Set ASPM bits in MPC2 register. */
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pci_update_config32(dev, 0xd4, ~(0x3 << 2),
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(1 << 4) | (0x2 << 2));
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/* Set unique clock exit latency in MPC register. */
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pci_update_config32(dev, 0xd8, ~(0x7 << 18), (0x7 << 18));
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switch (rp) {
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case 1:
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pcie_add_0x0202000_iobp(0xe9002440);
|
|
break;
|
|
case 2:
|
|
pcie_add_0x0202000_iobp(0xe9002640);
|
|
break;
|
|
case 3:
|
|
pcie_add_0x0202000_iobp(0xe9000840);
|
|
break;
|
|
case 4:
|
|
pcie_add_0x0202000_iobp(0xe9000a40);
|
|
break;
|
|
case 5:
|
|
pcie_add_0x0202000_iobp(0xe9000c40);
|
|
pcie_add_0x0202000_iobp(0xe9000e40);
|
|
pcie_add_0x0202000_iobp(0xe9001040);
|
|
pcie_add_0x0202000_iobp(0xe9001240);
|
|
break;
|
|
case 6:
|
|
/* Update IOBP based on lane ownership. */
|
|
if (rpc.pin_ownership & (1 << 4))
|
|
pcie_add_0x0202000_iobp(0xea002040);
|
|
if (rpc.pin_ownership & (1 << 5))
|
|
pcie_add_0x0202000_iobp(0xea002240);
|
|
if (rpc.pin_ownership & (1 << 6))
|
|
pcie_add_0x0202000_iobp(0xea002440);
|
|
if (rpc.pin_ownership & (1 << 7))
|
|
pcie_add_0x0202000_iobp(0xea002640);
|
|
break;
|
|
}
|
|
|
|
pci_update_config32(dev, 0x338, ~(1 << 26), 0);
|
|
}
|
|
|
|
/* Enable LTR in Root Port. Disable OBFF. */
|
|
pci_update_config32(dev, 0x64, ~(1 << 11) & ~(3 << 18), (1 << 11));
|
|
pci_update_config32(dev, 0x68, ~(1 << 10), (1 << 10));
|
|
|
|
pci_update_config32(dev, 0x318, ~(0xffff << 16), (0x1414 << 16));
|
|
|
|
/* Set L1 exit latency in LCAP register. */
|
|
if (!do_aspm && (pci_read_config8(dev, 0xf5) & 0x1))
|
|
pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x4 << 15));
|
|
else
|
|
pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x2 << 15));
|
|
|
|
pci_update_config32(dev, 0x314, 0x0, 0x743a361b);
|
|
|
|
/* Set Common Clock Exit Latency in MPC register. */
|
|
pci_update_config32(dev, 0xd8, ~(0x7 << 15), (0x3 << 15));
|
|
|
|
pci_update_config32(dev, 0x33c, ~0x00ffffff, 0x854d74);
|
|
|
|
/* Set Invalid Receive Range Check Enable in MPC register. */
|
|
pci_update_config32(dev, 0xd8, ~0, (1 << 25));
|
|
|
|
pci_update_config8(dev, 0xf5, 0x0f, 0);
|
|
|
|
/* Set AER Extended Cap ID to 01h and Next Cap Pointer to 200h. */
|
|
if (CONFIG(PCIEXP_AER))
|
|
pci_update_config32(dev, 0x100, ~(1 << 29) & ~0xfffff,
|
|
(1 << 29) | 0x10001);
|
|
else
|
|
pci_update_config32(dev, 0x100, ~(1 << 29) & ~0xfffff,
|
|
(1 << 29));
|
|
|
|
/* Set L1 Sub-State Cap ID to 1Eh and Next Cap Pointer to None. */
|
|
if (CONFIG(PCIEXP_L1_SUB_STATE))
|
|
pci_update_config32(dev, 0x200, ~0xfffff, 0x001e);
|
|
else
|
|
pci_update_config32(dev, 0x200, ~0xfffff, 0);
|
|
|
|
pci_update_config32(dev, 0x320, ~(3 << 20) & ~(7 << 6),
|
|
(1 << 20) | (3 << 6));
|
|
/* Enable Relaxed Order from Root Port. */
|
|
pci_update_config32(dev, 0x320, ~(3 << 23), (3 << 23));
|
|
|
|
if (rp == 1 || rp == 5 || rp == 6)
|
|
pci_update_config8(dev, 0xf7, ~0xc, 0);
|
|
|
|
/* Set EOI forwarding disable. */
|
|
pci_update_config32(dev, 0xd4, ~0, (1 << 1));
|
|
|
|
/* Read and write back write-once capability registers. */
|
|
pci_update_config32(dev, 0x34, ~0, 0);
|
|
pci_update_config32(dev, 0x40, ~0, 0);
|
|
pci_update_config32(dev, 0x80, ~0, 0);
|
|
pci_update_config32(dev, 0x90, ~0, 0);
|
|
}
|
|
|
|
static void pch_pcie_init(struct device *dev)
|
|
{
|
|
u16 reg16;
|
|
u32 reg32;
|
|
|
|
printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n");
|
|
|
|
/* Enable SERR */
|
|
reg32 = pci_read_config32(dev, PCI_COMMAND);
|
|
reg32 |= PCI_COMMAND_SERR;
|
|
pci_write_config32(dev, PCI_COMMAND, reg32);
|
|
|
|
/* Enable Bus Master */
|
|
reg32 = pci_read_config32(dev, PCI_COMMAND);
|
|
reg32 |= PCI_COMMAND_MASTER;
|
|
pci_write_config32(dev, PCI_COMMAND, reg32);
|
|
|
|
/* Set Cache Line Size to 0x10 */
|
|
pci_write_config8(dev, 0x0c, 0x10);
|
|
|
|
reg16 = pci_read_config16(dev, 0x3e);
|
|
reg16 &= ~(1 << 0); /* disable parity error response */
|
|
reg16 |= (1 << 2); /* ISA enable */
|
|
pci_write_config16(dev, 0x3e, reg16);
|
|
|
|
#ifdef EVEN_MORE_DEBUG
|
|
reg32 = pci_read_config32(dev, 0x20);
|
|
printk(BIOS_SPEW, " MBL = 0x%08x\n", reg32);
|
|
reg32 = pci_read_config32(dev, 0x24);
|
|
printk(BIOS_SPEW, " PMBL = 0x%08x\n", reg32);
|
|
reg32 = pci_read_config32(dev, 0x28);
|
|
printk(BIOS_SPEW, " PMBU32 = 0x%08x\n", reg32);
|
|
reg32 = pci_read_config32(dev, 0x2c);
|
|
printk(BIOS_SPEW, " PMLU32 = 0x%08x\n", reg32);
|
|
#endif
|
|
|
|
/* Clear errors in status registers */
|
|
reg16 = pci_read_config16(dev, 0x06);
|
|
pci_write_config16(dev, 0x06, reg16);
|
|
reg16 = pci_read_config16(dev, 0x1e);
|
|
pci_write_config16(dev, 0x1e, reg16);
|
|
}
|
|
|
|
static void pch_pcie_enable(struct device *dev)
|
|
{
|
|
/* Add this device to the root port config structure. */
|
|
root_port_init_config(dev);
|
|
|
|
/* Check to see if this Root Port should be disabled. */
|
|
root_port_check_disable(dev);
|
|
|
|
/* Power Management init before enumeration */
|
|
if (dev->enabled)
|
|
pch_pcie_early(dev);
|
|
|
|
/*
|
|
* When processing the last PCIe root port we can now
|
|
* update the Root Port Function Number and Hide register.
|
|
*/
|
|
if (root_port_is_last(dev))
|
|
root_port_commit_config();
|
|
}
|
|
|
|
static void pcie_set_L1_ss_max_latency(struct device *dev, unsigned int off)
|
|
{
|
|
/* Set max snoop and non-snoop latency for Broadwell */
|
|
pci_write_config32(dev, off,
|
|
PCIE_LTR_MAX_NO_SNOOP_LATENCY_3146US << 16 |
|
|
PCIE_LTR_MAX_SNOOP_LATENCY_3146US);
|
|
}
|
|
|
|
static struct pci_operations pcie_ops = {
|
|
.set_subsystem = pci_dev_set_subsystem,
|
|
.set_L1_ss_latency = pcie_set_L1_ss_max_latency,
|
|
};
|
|
|
|
static struct device_operations device_ops = {
|
|
.read_resources = pci_bus_read_resources,
|
|
.set_resources = pci_dev_set_resources,
|
|
.enable_resources = pci_bus_enable_resources,
|
|
.init = pch_pcie_init,
|
|
.enable = pch_pcie_enable,
|
|
.scan_bus = pciexp_scan_bridge,
|
|
.ops_pci = &pcie_ops,
|
|
};
|
|
|
|
static const unsigned short pcie_device_ids[] = {
|
|
/* Lynxpoint-LP */
|
|
0x9c10, 0x9c12, 0x9c14, 0x9c16, 0x9c18, 0x9c1a,
|
|
/* WildcatPoint */
|
|
0x9c90, 0x9c92, 0x9c94, 0x9c96, 0x9c98, 0x9c9a, 0x2448,
|
|
0
|
|
};
|
|
|
|
static const struct pci_driver pch_pcie __pci_driver = {
|
|
.ops = &device_ops,
|
|
.vendor = PCI_VENDOR_ID_INTEL,
|
|
.devices = pcie_device_ids,
|
|
};
|