237 lines
8.3 KiB
C
237 lines
8.3 KiB
C
/*
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* inteltool - dump all registers on an Intel CPU + chipset based system.
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*
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* Copyright (C) 2008-2010 by coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <inttypes.h>
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#include "inteltool.h"
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static const io_register_t sandybridge_mch_registers[] = {
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/* Channel 0 */
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{ 0x4000, 4, "TC_DBP_C0" }, // Timing of DDR Bin Parameters
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{ 0x4004, 4, "TC_RAP_C0" }, // Timing of DDR Regular Access Parameters
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{ 0x4028, 4, "SC_IO_LATENCY_C0" }, // IO Latency Configuration
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{ 0x42A4, 4, "TC_SRFTP_C0" }, // Self-Refresh Timing Parameters
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{ 0x40B0, 4, "PM_PDWN_config_C0" }, // Power-down Configuration
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{ 0x4294, 4, "TC_RFP_C0" }, // Refresh Parameters
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{ 0x4298, 4, "TC_RFTP_C0" }, // Refresh Timing Parameters
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/* Channel 1 */
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{ 0x4400, 4, "TC_DBP_C1" }, // Timing of DDR Bin Parameters
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{ 0x4404, 4, "TC_RAP_C1" }, // Timing of DDR Regular Access Parameters
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{ 0x4428, 4, "SC_IO_LATENCY_C1" }, // IO Latency Configuration
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{ 0x46A4, 4, "TC_SRFTP_C1" }, // Self-Refresh Timing Parameters
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{ 0x44B0, 4, "PM_PDWN_config_C1" }, // Power-down Configuration
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{ 0x4694, 4, "TC_RFP_C1" }, // Refresh Parameters
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{ 0x4698, 4, "TC_RFTP_C1" }, // Refresh Timing Parameters
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/* Integrated Memory Peripheral Hub (IMPH) */
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{ 0x740C, 4, "CRDTCTL3" }, // Credit Control 3
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/* Common Registers */
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{ 0x5000, 4, "MAD_CHNL" }, // Address decoder Channel Configuration
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{ 0x5004, 4, "MAD_DIMM_ch0" }, // Address Decode Channel 0
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{ 0x5008, 4, "MAD_DIMM_ch1" }, // Address Decode Channel 1
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{ 0x5060, 4, "PM_SREF_config" }, // Self Refresh Configuration
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/* MMIO Registers Broadcast Group */
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{ 0x4CB0, 4, "PM_PDWN_config" }, // Power-down Configuration
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{ 0x4F84, 4, "PM_CMD_PWR" }, // Power Management Command Power
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{ 0x4F88, 4, "PM_BW_LIMIT_config" }, // BW Limit Configuration
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{ 0x4F8C, 4, "RESERVED" }, // Reserved, default value - 0xFF1D1519
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/* PCU MCHBAR Registers */
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{ 0x5880, 4, "MEM_TRML_ESTIMATION_CONFIG" }, // Memory Thermal Estimation Configuration
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{ 0x5884, 4, "RESERVED" }, // Reserved
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{ 0x5888, 4, "MEM_TRML_THRESHOLDS_CONFIG" }, // Memory Thermal Thresholds Configuration
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{ 0x58A0, 4, "MEM_TRML_STATUS_REPORT" }, // Memory Thermal Status Report
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{ 0x58A4, 4, "MEM_TRML_TEMPERATURE_REPORT" }, // Memory Thermal Temperature Report
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{ 0x58A8, 4, "MEM_TRML_INTERRUPT" }, // Memory Thermal Interrupt
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{ 0x5948, 4, "GT_PERF_STATUS" }, // GT Performance Status
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{ 0x5998, 4, "RP_STATE_CAP" }, // RP State Capability
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{ 0x5D10, 8, "SSKPD" }, // Sticky Scratchpad Data
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};
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/*
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* (G)MCH MMIO Config Space
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*/
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int print_mchbar(struct pci_dev *nb, struct pci_access *pacc)
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{
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int i, size = (16 * 1024);
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volatile uint8_t *mchbar;
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uint64_t mchbar_phys;
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const io_register_t *mch_registers = NULL;
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struct pci_dev *nb_device6; /* "overflow device" on i865 */
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uint16_t pcicmd6;
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printf("\n============= MCHBAR ============\n\n");
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switch (nb->device_id) {
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case PCI_DEVICE_ID_INTEL_82865:
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/*
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* On i865, the memory access enable/disable bit (MCHBAREN on
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* i945/i965) is not in the MCHBAR (i945/i965) register but in
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* the PCICMD6 register. BAR6 and PCICMD6 reside on device 6.
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*
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* The actual base address is in BAR6 on i865 where on
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* i945/i965 the base address is in MCHBAR.
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*/
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nb_device6 = pci_get_dev(pacc, 0, 0, 0x06, 0); /* Device 6 */
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mchbar_phys = pci_read_long(nb_device6, 0x10); /* BAR6 */
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pcicmd6 = pci_read_long(nb_device6, 0x04); /* PCICMD6 */
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/* Try to enable Memory Access Enable (MAE). */
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if (!(pcicmd6 & (1 << 1))) {
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printf("Access to BAR6 is currently disabled, "
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"attempting to enable.\n");
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pci_write_long(nb_device6, 0x04, pcicmd6 | (1 << 1));
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if (pci_read_long(nb_device6, 0x04) & (1 << 1))
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printf("Enabled successfully.\n");
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else
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printf("Enable FAILED!\n");
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}
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mchbar_phys &= 0xfffff000; /* Bits 31:12 from BAR6 */
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break;
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case PCI_DEVICE_ID_INTEL_82915:
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case PCI_DEVICE_ID_INTEL_82945GM:
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case PCI_DEVICE_ID_INTEL_82945GSE:
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case PCI_DEVICE_ID_INTEL_82945P:
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case PCI_DEVICE_ID_INTEL_82975X:
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mchbar_phys = pci_read_long(nb, 0x44) & 0xfffffffe;
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break;
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case PCI_DEVICE_ID_INTEL_82965PM:
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case PCI_DEVICE_ID_INTEL_82Q35:
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case PCI_DEVICE_ID_INTEL_82G33:
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case PCI_DEVICE_ID_INTEL_82Q33:
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mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe;
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mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
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break;
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case PCI_DEVICE_ID_INTEL_82946:
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case PCI_DEVICE_ID_INTEL_82Q965:
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case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
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case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
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mchbar_phys = pci_read_long(nb, 0x48);
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/* Test if bit 0 of the MCHBAR reg is 1 to enable memory reads.
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* If it isn't, try to set it. This may fail, because there is
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* some bit that locks that bit, and isn't in the public
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* datasheets.
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*/
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if(!(mchbar_phys & 1))
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{
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printf("Access to the MCHBAR is currently disabled, "
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"attempting to enable.\n");
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mchbar_phys |= 0x1;
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pci_write_long(nb, 0x48, mchbar_phys);
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if(pci_read_long(nb, 0x48) & 1)
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printf("Enabled successfully.\n");
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else
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printf("Enable FAILED!\n");
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}
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mchbar_phys &= 0xfffffffe;
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mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
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break;
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case PCI_DEVICE_ID_INTEL_82443LX:
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case PCI_DEVICE_ID_INTEL_82443BX:
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case PCI_DEVICE_ID_INTEL_82810:
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case PCI_DEVICE_ID_INTEL_82810E_DC:
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case PCI_DEVICE_ID_INTEL_82810_DC:
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case PCI_DEVICE_ID_INTEL_82830M:
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printf("This northbridge does not have MCHBAR.\n");
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return 1;
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case PCI_DEVICE_ID_INTEL_82X4X:
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case PCI_DEVICE_ID_INTEL_82X38:
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case PCI_DEVICE_ID_INTEL_32X0:
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mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe;
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mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
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break;
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case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN:
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mchbar_phys = pci_read_long(nb, 0x48);
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mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
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mchbar_phys &= 0x0000000fffffc000UL; /* 35:14 */
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mch_registers = NULL; /* No public documentation */
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break;
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case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN:
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mch_registers = sandybridge_mch_registers;
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size = ARRAY_SIZE(sandybridge_mch_registers);
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case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN: /* pretty printing not implemented yet */
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mchbar_phys = pci_read_long(nb, 0x48);
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mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
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mchbar_phys &= 0x0000007fffff8000UL; /* 38:15 */
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break;
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default:
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printf("Error: Dumping MCHBAR on this northbridge is not (yet) supported.\n");
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return 1;
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}
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mchbar = map_physical(mchbar_phys, size);
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if (mchbar == NULL) {
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if (nb->device_id == PCI_DEVICE_ID_INTEL_82865)
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perror("Error mapping BAR6");
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else
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perror("Error mapping MCHBAR");
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exit(1);
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}
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if (nb->device_id == PCI_DEVICE_ID_INTEL_82865)
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printf("BAR6 = 0x%08" PRIx64 " (MEM)\n\n", mchbar_phys);
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else
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printf("MCHBAR = 0x%08" PRIx64 " (MEM)\n\n", mchbar_phys);
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if (mch_registers != NULL) {
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printf("%d registers:\n", size);
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for (i = 0; i < size; i++) {
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switch (mch_registers[i].size) {
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case 8:
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printf("mchbase+0x%04x: 0x%016llx (%s)\n",
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mch_registers[i].addr,
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*(uint64_t *)(mchbar+mch_registers[i].addr),
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mch_registers[i].name);
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break;
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case 4:
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printf("mchbase+0x%04x: 0x%08x (%s)\n",
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mch_registers[i].addr,
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*(uint32_t *)(mchbar+mch_registers[i].addr),
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mch_registers[i].name);
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break;
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case 2:
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printf("mchbase+0x%04x: 0x%04x (%s)\n",
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mch_registers[i].addr,
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*(uint16_t *)(mchbar+mch_registers[i].addr),
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mch_registers[i].name);
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break;
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case 1:
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printf("mchbase+0x%04x: 0x%02x (%s)\n",
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mch_registers[i].addr,
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*(uint8_t *)(mchbar+mch_registers[i].addr),
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mch_registers[i].name);
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break;
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}
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}
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} else {
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for (i = 0; i < size; i += 4) {
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if (*(uint32_t *)(mchbar + i))
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printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(mchbar+i));
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}
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}
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unmap_physical((void *)mchbar, size);
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return 0;
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}
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