d157b3e1e0
The callers don't necessarily check return value of function. Make sure the parameters are not left uninitialised in that case. Change-Id: Ic02db2d35b2ec88506320e7df609940de4aef005 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34708 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
107 lines
2.6 KiB
C
107 lines
2.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 - 2017 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <cbmem.h>
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#include <assert.h>
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#include <cpu/x86/smm.h>
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#include <device/device.h>
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#include <device/pci_def.h>
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#include <device/pci_ops.h>
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#include <soc/pci_devs.h>
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#include <soc/systemagent.h>
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#include <lib.h>
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/* Returns base of requested region encoded in the system agent. */
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static inline uintptr_t system_agent_region_base(size_t reg)
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{
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#if defined(__SIMPLE_DEVICE__)
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pci_devfn_t dev = SA_DEV_ROOT;
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#else
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struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
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#endif
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/* All regions concerned for have 1 MiB alignment. */
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return ALIGN_DOWN(pci_read_config32(dev, reg), 1 * MiB);
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}
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/* Returns min power of 2 >= size */
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static inline u32 power_of_2(u32 size)
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{
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return size ? 1 << (1 + log2(size - 1)) : 0;
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}
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u32 top_of_32bit_ram(void)
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{
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u32 iqat_region_size = 0;
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u32 tseg_region_size = system_agent_region_base(TOLUD) -
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system_agent_region_base(TSEGMB);
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/*
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* Add IQAT region size if enabled.
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*/
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#if CONFIG(IQAT_ENABLE)
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iqat_region_size = CONFIG_IQAT_MEMORY_REGION_SIZE;
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#endif
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return system_agent_region_base(TOLUD) -
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power_of_2(iqat_region_size + tseg_region_size);
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}
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void *cbmem_top(void) { return (void *)top_of_32bit_ram(); }
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static inline uintptr_t smm_region_start(void)
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{
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return system_agent_region_base(TSEGMB);
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}
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static inline size_t smm_region_size(void)
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{
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return system_agent_region_base(TOLUD) - smm_region_start();
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}
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void smm_region(uintptr_t *start, size_t *size)
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{
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*start = smm_region_start();
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*size = smm_region_size();
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}
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int smm_subregion(int sub, uintptr_t *start, size_t *size)
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{
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uintptr_t sub_base;
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size_t sub_size;
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const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
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smm_region(&sub_base, &sub_size);
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assert(sub_size > CONFIG_SMM_RESERVED_SIZE);
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switch (sub) {
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case SMM_SUBREGION_HANDLER:
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/* Handler starts at the base of TSEG. */
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sub_size -= cache_size;
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break;
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case SMM_SUBREGION_CACHE:
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/* External cache is in the middle of TSEG. */
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sub_base += sub_size - cache_size;
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sub_size = cache_size;
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break;
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default:
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*start = 0;
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*size = 0;
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return -1;
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}
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*start = sub_base;
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*size = sub_size;
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return 0;
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}
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