5239ba2f8f
In some cases, we want a ram_check that does not die and does not clobber the terminal with useless output that slows us down a lot. Usage examples include Checking if the RAM is up at the start of raminit, or checking if each rank is accessible as it is being initialized. As with all other ram_checks, this is more of a "Is my DRAM properly configured?" test, which is exactly what we want for something to use during memory initialization. Change-Id: I95d8d9a2ce1e29c74ef97b90aba0773f88ae832c Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/3416 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
279 lines
6.1 KiB
C
279 lines
6.1 KiB
C
#include <stdint.h>
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#include <lib.h> /* Prototypes */
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#include <console/console.h>
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static void write_phys(unsigned long addr, u32 value)
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{
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// Assembler in lib/ is very ugly. But we properly guarded
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// it so let's obey this one for now
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#if CONFIG_SSE2
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asm volatile(
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"movnti %1, (%0)"
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: /* outputs */
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: "r" (addr), "r" (value) /* inputs */
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#ifndef __GNUC__ /* GCC does not like empty clobbers? */
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: /* clobbers */
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#endif
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);
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#else
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volatile unsigned long *ptr;
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ptr = (void *)addr;
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*ptr = value;
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#endif
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}
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static u32 read_phys(unsigned long addr)
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{
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volatile unsigned long *ptr;
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ptr = (void *)addr;
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return *ptr;
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}
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static void phys_memory_barrier(void)
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{
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#if CONFIG_SSE2
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// Needed for movnti
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asm volatile (
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"sfence"
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::
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#ifdef __GNUC__ /* ROMCC does not like memory clobbers */
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: "memory"
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#endif
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);
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#else
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#ifdef __GNUC__ /* ROMCC does not like empty asm statements */
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asm volatile ("" ::: "memory");
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#endif
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#endif
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}
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/**
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* Rotate ones test pattern that access every bit on a 128bit wide
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* memory bus. To test most address lines, addresses are scattered
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* using 256B, 4kB and 64kB increments.
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*
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* @idx Index to test pattern (0=<idx<0x400)
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* @addr Memory to access on @idx
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* @value Value to write or read at @addr
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*/
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static inline void test_pattern(unsigned short int idx,
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unsigned long *addr, unsigned long *value)
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{
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uint8_t j, k;
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k = (idx >> 8) + 1;
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j = (idx >> 4) & 0x0f;
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*addr = idx & 0x0f;
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*addr |= j << (4*k);
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*value = 0x01010101 << (j & 7);
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if (j & 8)
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*value = ~(*value);
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}
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/**
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* Simple write-read-verify memory test. See console debug output for
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* any dislocated bytes.
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*
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* @start System memory offset, aligned to 128bytes
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*/
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static int ram_bitset_nodie(unsigned long start)
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{
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unsigned long addr, value, value2;
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unsigned short int idx;
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unsigned char failed, failures;
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uint8_t verbose = 0;
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#if !defined(__ROMCC__)
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printk(BIOS_DEBUG, "DRAM bitset write: 0x%08lx\n", start);
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#else
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print_debug("DRAM bitset write: 0x");
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print_debug_hex32(start);
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print_debug("\n");
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#endif
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for (idx=0; idx<0x400; idx+=4) {
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test_pattern(idx, &addr, &value);
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write_phys(start + addr, value);
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}
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/* Make sure we don't read before we wrote */
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phys_memory_barrier();
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#if !defined(__ROMCC__)
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printk(BIOS_DEBUG, "DRAM bitset verify: 0x%08lx\n", start);
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#else
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print_debug("DRAM bitset verify: 0x");
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print_debug_hex32(start);
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print_debug("\n");
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#endif
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failures = 0;
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for (idx=0; idx<0x400; idx+=4) {
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test_pattern(idx, &addr, &value);
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value2 = read_phys(start + addr);
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failed = (value2 != value);
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failures |= failed;
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if (failed && !verbose) {
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#if !defined(__ROMCC__)
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printk(BIOS_ERR, "0x%08lx wr: 0x%08lx rd: 0x%08lx FAIL\n",
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start + addr, value, value2);
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#else
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print_err_hex32(start + addr);
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print_err(" wr: 0x");
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print_err_hex32(value);
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print_err(" rd: 0x");
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print_err_hex32(value2);
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print_err(" FAIL\n");
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#endif
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}
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if (verbose) {
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#if !defined(__ROMCC__)
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if ((addr & 0x0f) == 0)
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printk(BIOS_DEBUG, "%08lx wr: %08lx rd:",
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start + addr, value);
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if (failed)
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printk(BIOS_DEBUG, " %08lx!", value2);
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else
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printk(BIOS_DEBUG, " %08lx ", value2);
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if ((addr & 0x0f) == 0xc)
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printk(BIOS_DEBUG, "\n");
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#else
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if ((addr & 0x0f) == 0) {
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print_dbg_hex32(start + addr);
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print_dbg(" wr: ");
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print_dbg_hex32(value);
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print_dbg(" rd: ");
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}
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print_dbg_hex32(value2);
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if (failed)
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print_dbg("! ");
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else
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print_dbg(" ");
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if ((addr & 0x0f) == 0xc)
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print_dbg("\n");
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#endif
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}
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}
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if (failures) {
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post_code(0xea);
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#if !defined(__ROMCC__)
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printk(BIOS_DEBUG, "\nDRAM did _NOT_ verify!\n");
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#else
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print_debug("\nDRAM did _NOT_ verify!\n");
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#endif
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return 1;
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}
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else {
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#if !defined(__ROMCC__)
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printk(BIOS_DEBUG, "\nDRAM range verified.\n");
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#else
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print_debug("\nDRAM range verified.\n");
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return 0;
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#endif
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}
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return 0;
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}
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void ram_check(unsigned long start, unsigned long stop)
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{
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/*
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* This is much more of a "Is my DRAM properly configured?"
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* test than a "Is my DRAM faulty?" test. Not all bits
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* are tested. -Tyson
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*/
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#if !defined(__ROMCC__)
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printk(BIOS_DEBUG, "Testing DRAM at: %08lx\n", start);
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#else
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print_debug("Testing DRAM at: ");
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print_debug_hex32(start);
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print_debug("\n");
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#endif
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if (ram_bitset_nodie(start))
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die("DRAM ERROR");
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#if !defined(__ROMCC__)
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printk(BIOS_DEBUG, "Done.\n");
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#else
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print_debug("Done.\n");
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#endif
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}
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int ram_check_nodie(unsigned long start, unsigned long stop)
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{
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int ret;
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/*
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* This is much more of a "Is my DRAM properly configured?"
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* test than a "Is my DRAM faulty?" test. Not all bits
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* are tested. -Tyson
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*/
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#if !defined(__ROMCC__)
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printk(BIOS_DEBUG, "Testing DRAM at : %08lx\n", start);
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#else
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print_debug("Testing DRAM at : ");
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print_debug_hex32(start);
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print_debug("\n");
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#endif
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ret = ram_bitset_nodie(start);
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#if !defined(__ROMCC__)
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printk(BIOS_DEBUG, "Done.\n");
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#else
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print_debug("Done.\n");
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#endif
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return ret;
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}
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int ram_check_noprint_nodie(unsigned long start, unsigned long stop)
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{
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unsigned long addr, value, value2;
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unsigned short int idx;
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unsigned char failed, failures;
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for (idx=0; idx<0x400; idx+=4) {
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test_pattern(idx, &addr, &value);
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write_phys(start + addr, value);
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}
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/* Make sure we don't read before we wrote */
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phys_memory_barrier();
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failures = 0;
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for (idx=0; idx<0x400; idx+=4) {
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test_pattern(idx, &addr, &value);
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value2 = read_phys(start + addr);
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failed = (value2 != value);
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failures |= failed;
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}
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return failures;
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}
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void quick_ram_check(void)
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{
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int fail = 0;
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u32 backup;
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backup = read_phys(CONFIG_RAMBASE);
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write_phys(CONFIG_RAMBASE, 0x55555555);
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phys_memory_barrier();
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if (read_phys(CONFIG_RAMBASE) != 0x55555555)
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fail=1;
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write_phys(CONFIG_RAMBASE, 0xaaaaaaaa);
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phys_memory_barrier();
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if (read_phys(CONFIG_RAMBASE) != 0xaaaaaaaa)
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fail=1;
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write_phys(CONFIG_RAMBASE, 0x00000000);
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phys_memory_barrier();
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if (read_phys(CONFIG_RAMBASE) != 0x00000000)
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fail=1;
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write_phys(CONFIG_RAMBASE, 0xffffffff);
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phys_memory_barrier();
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if (read_phys(CONFIG_RAMBASE) != 0xffffffff)
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fail=1;
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write_phys(CONFIG_RAMBASE, backup);
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if (fail) {
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post_code(0xea);
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die("RAM INIT FAILURE!\n");
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}
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phys_memory_barrier();
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}
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