cd2aa47a34
These are only referenced inside auto-generated static.c files, and util/sconfig also generates the declarations automatically from source file pathnames. Change-Id: Id324790755095c36fbeb73a4d8f9d01cdf6409cb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34979 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
90 lines
2.6 KiB
C
90 lines
2.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* The devicetree parser expects chip.h to reside directly in the path
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* specified by the devicetree. */
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#ifndef _BAYTRAIL_CHIP_H_
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#define _BAYTRAIL_CHIP_H_
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#include <stdint.h>
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struct soc_intel_baytrail_config {
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uint8_t enable_xdp_tap;
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uint8_t sata_port_map;
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uint8_t sata_ahci;
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uint8_t ide_legacy_combined;
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uint8_t clkreq_enable;
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/* VR low power settings -- enable PS2 mode for gfx and core */
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int vnn_ps2_enable;
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int vcc_ps2_enable;
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/* Disable SLP_X stretching after SUS power well loss. */
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int disable_slp_x_stretch_sus_fail;
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/* USB Port Disable mask */
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uint16_t usb2_port_disable_mask;
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uint16_t usb3_port_disable_mask;
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/* USB routing */
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int usb_route_to_xhci;
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/* USB PHY settings specific to the board */
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uint32_t usb2_per_port_lane0;
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uint32_t usb2_per_port_rcomp_hs_pullup0;
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uint32_t usb2_per_port_lane1;
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uint32_t usb2_per_port_rcomp_hs_pullup1;
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uint32_t usb2_per_port_lane2;
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uint32_t usb2_per_port_rcomp_hs_pullup2;
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uint32_t usb2_per_port_lane3;
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uint32_t usb2_per_port_rcomp_hs_pullup3;
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uint32_t usb2_comp_bg;
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/* LPE Audio Clock configuration. */
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int lpe_codec_clk_freq; /* 19 or 25 are valid. */
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int lpe_codec_clk_num; /* Platform clock pins. [0:5] are valid. */
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/* Native SD Card controller - override controller capabilities. */
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uint32_t sdcard_cap_low;
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uint32_t sdcard_cap_high;
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/* Enable devices in ACPI mode */
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int lpss_acpi_mode;
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int scc_acpi_mode;
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int lpe_acpi_mode;
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/* Allow PCIe devices to wake system from suspend. */
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int pcie_wake_enable;
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uint8_t gpu_pipea_port_select; /* Port select: 1=DP_B 2=DP_C */
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uint16_t gpu_pipea_power_on_delay;
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uint16_t gpu_pipea_light_on_delay;
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uint16_t gpu_pipea_power_off_delay;
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uint16_t gpu_pipea_light_off_delay;
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uint16_t gpu_pipea_power_cycle_delay;
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int gpu_pipea_pwm_freq_hz;
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uint8_t gpu_pipeb_port_select; /* Port select: 1=DP_B 2=DP_C */
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uint16_t gpu_pipeb_power_on_delay;
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uint16_t gpu_pipeb_light_on_delay;
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uint16_t gpu_pipeb_power_off_delay;
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uint16_t gpu_pipeb_light_off_delay;
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uint16_t gpu_pipeb_power_cycle_delay;
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int gpu_pipeb_pwm_freq_hz;
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int disable_ddr_2x_refresh_rate;
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};
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#endif /* _BAYTRAIL_CHIP_H_ */
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