coreboot-kgpe-d16/src/arch
Xiang Wang 21ed107958 riscv: add entry assembly file for RAMSTAGE
RAMSTAGE will revoke CAR/scratchpad, so stack and exception handling
needs to be moved to ddr memory. So add a assembly file to do this.

Change-Id: I58aa6ff911f385180bad6e026d3c3eace846e37d
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/28384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-05 10:04:57 +00:00
..
arm src/arch: Fix typo 2018-08-09 15:56:02 +00:00
arm64 arm64: Factor out common parts of romstage execution flow 2018-08-17 21:29:46 +00:00
mips arch: Retire cache_sync_instructions() from <arch/cache.h> (except arm) 2018-08-07 20:55:58 +00:00
power8 arch: Retire cache_sync_instructions() from <arch/cache.h> (except arm) 2018-08-07 20:55:58 +00:00
riscv riscv: add entry assembly file for RAMSTAGE 2018-09-05 10:04:57 +00:00
x86 acpi: Hide Chrome and coreboot specific devices 2018-08-28 15:14:42 +00:00