876cfe0ee2
Mainboards using Sabrina SoC will be using LP5 memory technology. Generate the initial set of SPDs for the existing LP5 memory parts. BUG=b:211510456 TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ibb43f26b36460290341c5ffcad1ef5a2ff1647c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
7 lines
199 B
Text
7 lines
199 B
Text
# Generated by:
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# util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
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MT62F512M32D2DR-031 WT:B,spd-1.hex
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MT62F1G32D4DR-031 WT:B,spd-2.hex
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H9JCNNNCP3MLYR-N6E,spd-2.hex
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K3LKBKB0BM-MGCP,spd-3.hex
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