Patrick Georgi 42f15054b1 memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere ... This is in preparation of a larger heap. I went for 2MB because why not? Change-Id: I51f999a10ba894a7f2f5fce224d30bf914107c38 Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>		2023-10-11 12:08:22 +00:00
..
include/soc
bootblock.c
cbmem.c	cbmem_top_chipset: Change the return value to uintptr_t	2022-11-18 16:00:45 +00:00
chip.c
clint.c
clock.c
ddrregs.h
Kconfig	soc/sifive/fu540/Kconfig: Fix opensbi platform	2023-08-04 14:04:13 +00:00
Makefile.inc
memlayout.ld	memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere	2023-10-11 12:08:22 +00:00
otp.c
regconfig-ctl.h
regconfig-phy.h
sdram.c
spi.c	soc/sifive/fu540: Remove space after a cast	2023-09-19 13:13:27 +00:00
spi_internal.h
uart.c
ux00ddr.h	soc/sifive/fu540: Remove space after a cast	2023-09-19 13:13:27 +00:00