e8e66f4763
Use shared gpio code from common folder. Bd82x6x's gpio.c and gpio.h is used by other southbridges as well and will be removed once it is unused. Change-Id: I8bd981c4696c174152cf41caefa6c083650d283a Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/13614 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
288 lines
8.4 KiB
C
288 lines
8.4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef STOUT_GPIO_H
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#define STOUT_GPIO_H
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#include <southbridge/intel/common/gpio.h>
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const struct pch_gpio_set1 pch_gpio_set1_mode = {
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.gpio0 = GPIO_MODE_GPIO, /* GPIO0 */
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.gpio1 = GPIO_MODE_GPIO, /* SIO_EXT_SMI# */
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.gpio2 = GPIO_MODE_NONE, /* NOT USED */
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.gpio3 = GPIO_MODE_NONE, /* NOT USED */
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.gpio4 = GPIO_MODE_NONE, /* NOT USED */
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.gpio5 = GPIO_MODE_GPIO, /* INTH# */
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.gpio6 = GPIO_MODE_GPIO, /* SIO_EXT_SCI# */
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.gpio7 = GPIO_MODE_GPIO, /* GE_SCR_WP# */
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.gpio8 = GPIO_MODE_NONE, /* NOT USED */
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.gpio9 = GPIO_MODE_NATIVE, /* USB_OC5# */
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.gpio10 = GPIO_MODE_NATIVE, /* USB_OC6# */
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.gpio11 = GPIO_MODE_NATIVE, /* SMBALERT# */
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.gpio12 = GPIO_MODE_GPIO, /* GPIO12 */
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.gpio13 = GPIO_MODE_GPIO, /* GPIO13 */
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.gpio14 = GPIO_MODE_NATIVE, /* USB_OC7# */
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.gpio15 = GPIO_MODE_GPIO, /* GPIO15 */
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.gpio16 = GPIO_MODE_GPIO, /* WWAN_LED_ON */
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.gpio17 = GPIO_MODE_GPIO, /* WLAN_LED_ON */
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.gpio18 = GPIO_MODE_NATIVE, /* PCIE_CLKREQ_WLAN# */
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.gpio19 = GPIO_MODE_GPIO, /* BBS_BIT0 */
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.gpio20 = GPIO_MODE_NATIVE, /* PCIE_CLKREQ_CARD# */
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.gpio21 = GPIO_MODE_GPIO, /* BT_DET# / TP29 */
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.gpio22 = GPIO_MODE_GPIO, /* MODEL_ID0 */
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.gpio23 = GPIO_MODE_GPIO, /* LCD_BK_OFF */
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.gpio24 = GPIO_MODE_NATIVE, /* GPIO24 */
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.gpio25 = GPIO_MODE_NATIVE, /* PCIE_REQ_WWAN# / TP89 */
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.gpio26 = GPIO_MODE_NATIVE, /* CLK_PCIE_REQ4# / TP59 */
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.gpio27 = GPIO_MODE_GPIO, /* MSATA_DTCT# */
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.gpio28 = GPIO_MODE_GPIO, /* PLL_ODVR_EN */
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.gpio29 = GPIO_MODE_GPIO, /* WLAN_AOAC_ON */
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.gpio30 = GPIO_MODE_NATIVE, /* SUS_PWR_ACK */
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.gpio31 = GPIO_MODE_NATIVE, /* AC_PRESENT */
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};
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const struct pch_gpio_set1 pch_gpio_set1_direction = {
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/*
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* Note: Only gpio configured as "gpio" or "none" need to have the
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* direction configured.
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*/
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.gpio0 = GPIO_DIR_OUTPUT,
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.gpio1 = GPIO_DIR_INPUT,
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.gpio2 = GPIO_DIR_INPUT,
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.gpio3 = GPIO_DIR_INPUT,
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.gpio4 = GPIO_DIR_INPUT,
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.gpio5 = GPIO_DIR_OUTPUT,
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.gpio6 = GPIO_DIR_INPUT,
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.gpio7 = GPIO_DIR_INPUT,
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.gpio8 = GPIO_DIR_INPUT,
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.gpio12 = GPIO_DIR_OUTPUT,
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.gpio13 = GPIO_DIR_OUTPUT,
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.gpio15 = GPIO_DIR_INPUT,
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.gpio16 = GPIO_DIR_OUTPUT,
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.gpio17 = GPIO_DIR_OUTPUT,
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.gpio19 = GPIO_DIR_OUTPUT,
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.gpio21 = GPIO_DIR_OUTPUT,
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.gpio22 = GPIO_DIR_INPUT,
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.gpio23 = GPIO_DIR_OUTPUT,
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.gpio27 = GPIO_DIR_INPUT,
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.gpio28 = GPIO_DIR_OUTPUT,
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.gpio29 = GPIO_DIR_OUTPUT,
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};
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const struct pch_gpio_set1 pch_gpio_set1_level = {
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/*
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* Note: Only gpio configured as "gpio" or "none" need to have the
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* level set.
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*/
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.gpio0 = GPIO_LEVEL_HIGH,
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.gpio1 = GPIO_LEVEL_LOW,
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.gpio2 = GPIO_LEVEL_LOW,
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.gpio3 = GPIO_LEVEL_LOW,
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.gpio4 = GPIO_LEVEL_LOW,
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.gpio5 = GPIO_LEVEL_HIGH,
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.gpio6 = GPIO_LEVEL_LOW,
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.gpio7 = GPIO_LEVEL_HIGH,
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.gpio8 = GPIO_LEVEL_LOW,
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.gpio12 = GPIO_LEVEL_LOW,
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.gpio13 = GPIO_LEVEL_LOW,
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.gpio15 = GPIO_LEVEL_LOW,
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.gpio16 = GPIO_LEVEL_HIGH,
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.gpio17 = GPIO_LEVEL_LOW,
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.gpio19 = GPIO_LEVEL_LOW,
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.gpio21 = GPIO_LEVEL_LOW,
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.gpio22 = GPIO_LEVEL_LOW,
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.gpio23 = GPIO_LEVEL_LOW,
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.gpio27 = GPIO_LEVEL_LOW,
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.gpio28 = GPIO_LEVEL_HIGH,
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.gpio29 = GPIO_LEVEL_HIGH,
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};
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const struct pch_gpio_set1 pch_gpio_set1_invert = {
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.gpio1 = GPIO_INVERT,
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.gpio6 = GPIO_INVERT,
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.gpio8 = GPIO_INVERT,
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};
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const struct pch_gpio_set2 pch_gpio_set2_mode = {
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.gpio32 = GPIO_MODE_NATIVE, /* PCI_CLKRUN# */
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.gpio33 = GPIO_MODE_GPIO, /* GPIO33 */
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.gpio34 = GPIO_MODE_GPIO, /* CCD_ON */
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.gpio35 = GPIO_MODE_GPIO, /* BT_ON */
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.gpio36 = GPIO_MODE_NONE, /* NOT USED */
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.gpio37 = GPIO_MODE_NONE, /* NOT USED */
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.gpio38 = GPIO_MODE_NONE, /* NOT USED */
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.gpio39 = GPIO_MODE_NONE, /* NOT USED */
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.gpio40 = GPIO_MODE_GPIO, /* USB_OC1# */
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.gpio41 = GPIO_MODE_GPIO, /* USB_OC2# */
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.gpio42 = GPIO_MODE_NATIVE, /* USB_OC3# */
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.gpio43 = GPIO_MODE_NATIVE, /* USB_OC4_AUO4# */
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.gpio44 = GPIO_MODE_NATIVE, /* PCIE_CLKREQ_LAN# */
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.gpio45 = GPIO_MODE_NATIVE, /* PCIECLKRQ6# / TP48 */
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.gpio46 = GPIO_MODE_NATIVE, /* PCIECLKRQ7# / TP57 */
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.gpio47 = GPIO_MODE_NATIVE, /* CLK_PEGA_REQ# */
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.gpio48 = GPIO_MODE_GPIO, /* DIS_BT_ON# */
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.gpio49 = GPIO_MODE_GPIO, /* GPIO49 */
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.gpio50 = GPIO_MODE_NATIVE, /* PCI_REQ1# */
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.gpio51 = GPIO_MODE_GPIO, /* BBS_BIT1 */
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.gpio52 = GPIO_MODE_NATIVE, /* PCI_REQ2# */
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.gpio53 = GPIO_MODE_GPIO, /* PWM_SELECT# / TP44 */
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.gpio54 = GPIO_MODE_GPIO, /* PCI_REQ3# */
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.gpio55 = GPIO_MODE_NATIVE, /* PCI_GNT3# */
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.gpio56 = GPIO_MODE_NATIVE, /* CLK_PEGB_REQ# / TP60 */
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.gpio57 = GPIO_MODE_GPIO, /* PCH_GPIO57 */
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.gpio58 = GPIO_MODE_NATIVE, /* SMB_ME1_CLK */
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.gpio59 = GPIO_MODE_GPIO, /* USB_OC0_1# */
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.gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */
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.gpio61 = GPIO_MODE_GPIO, /* LPCPD# */
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.gpio62 = GPIO_MODE_NATIVE, /* PCH_SUSCLK_L / TP54 */
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.gpio63 = GPIO_MODE_NATIVE, /* TP51 */
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};
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const struct pch_gpio_set2 pch_gpio_set2_direction = {
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/*
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* Note: Only gpio configured as "gpio" or "none" need to have the
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* direction configured.
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*/
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.gpio33 = GPIO_DIR_OUTPUT,
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.gpio34 = GPIO_DIR_OUTPUT,
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.gpio35 = GPIO_DIR_OUTPUT,
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.gpio36 = GPIO_DIR_INPUT,
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.gpio37 = GPIO_DIR_INPUT,
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.gpio38 = GPIO_DIR_INPUT,
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.gpio39 = GPIO_DIR_INPUT,
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.gpio40 = GPIO_DIR_INPUT,
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.gpio41 = GPIO_DIR_INPUT,
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.gpio48 = GPIO_DIR_OUTPUT,
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.gpio49 = GPIO_DIR_INPUT,
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.gpio51 = GPIO_DIR_OUTPUT,
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.gpio53 = GPIO_DIR_OUTPUT,
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.gpio54 = GPIO_DIR_INPUT,
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.gpio57 = GPIO_DIR_INPUT,
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.gpio59 = GPIO_DIR_INPUT,
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.gpio60 = GPIO_DIR_OUTPUT,
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.gpio61 = GPIO_DIR_OUTPUT,
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};
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const struct pch_gpio_set2 pch_gpio_set2_level = {
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/*
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* Note: Only gpio configured as "gpio" or "none" need to have the
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* level set.
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*/
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.gpio33 = GPIO_LEVEL_LOW,
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.gpio34 = GPIO_LEVEL_HIGH,
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.gpio35 = GPIO_LEVEL_HIGH,
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.gpio36 = GPIO_LEVEL_LOW,
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.gpio37 = GPIO_LEVEL_LOW,
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.gpio38 = GPIO_LEVEL_LOW,
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.gpio39 = GPIO_LEVEL_LOW,
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.gpio40 = GPIO_LEVEL_HIGH,
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.gpio41 = GPIO_LEVEL_LOW,
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.gpio48 = GPIO_LEVEL_LOW,
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.gpio49 = GPIO_LEVEL_HIGH,
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.gpio51 = GPIO_LEVEL_HIGH,
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.gpio53 = GPIO_LEVEL_HIGH,
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.gpio54 = GPIO_LEVEL_LOW,
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.gpio57 = GPIO_LEVEL_LOW,
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.gpio59 = GPIO_LEVEL_HIGH,
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.gpio60 = GPIO_LEVEL_HIGH,
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.gpio61 = GPIO_LEVEL_LOW,
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};
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const struct pch_gpio_set3 pch_gpio_set3_mode = {
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.gpio64 = GPIO_MODE_GPIO, /* CLK_FLEX0 / TP38 */
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.gpio65 = GPIO_MODE_GPIO, /* CLK_FLEX1 / TP45 */
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.gpio66 = GPIO_MODE_GPIO, /* CLK_FLEX2 / TP83 */
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.gpio67 = GPIO_MODE_GPIO, /* CLK_FLEX3 / TP82 */
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.gpio68 = GPIO_MODE_GPIO, /* WWAN_DTCT# */
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.gpio69 = GPIO_MODE_GPIO, /* GPIO69 */
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.gpio70 = GPIO_MODE_GPIO, /* WLAN_OFF# */
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.gpio71 = GPIO_MODE_GPIO, /* WWAN_OFF# */
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.gpio72 = GPIO_MODE_GPIO, /* PM_BATLOW# */
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.gpio73 = GPIO_MODE_NATIVE, /* PCIECLKRQ0# / TP39 */
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.gpio74 = GPIO_MODE_NATIVE, /* SML1ALERT#_R / TP56 */
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.gpio75 = GPIO_MODE_NATIVE, /* SMB_ME1_DAT */
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};
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const struct pch_gpio_set3 pch_gpio_set3_direction = {
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/*
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* Note: Only gpio configured as "gpio" or "none" need to have the
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* direction configured.
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*/
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.gpio64 = GPIO_DIR_OUTPUT,
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.gpio65 = GPIO_DIR_OUTPUT,
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.gpio66 = GPIO_DIR_OUTPUT,
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.gpio67 = GPIO_DIR_INPUT,
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.gpio68 = GPIO_DIR_INPUT,
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.gpio69 = GPIO_DIR_OUTPUT,
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.gpio70 = GPIO_DIR_OUTPUT,
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.gpio71 = GPIO_DIR_OUTPUT,
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.gpio72 = GPIO_DIR_OUTPUT,
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};
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const struct pch_gpio_set3 pch_gpio_set3_level = {
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/*
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* Note: Only gpio configured as "gpio" or "none" need to have the
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* level set.
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*/
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.gpio64 = GPIO_LEVEL_HIGH,
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.gpio65 = GPIO_LEVEL_LOW,
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.gpio66 = GPIO_LEVEL_HIGH,
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.gpio67 = GPIO_LEVEL_LOW,
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.gpio68 = GPIO_LEVEL_HIGH,
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.gpio69 = GPIO_LEVEL_LOW,
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.gpio70 = GPIO_LEVEL_HIGH,
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.gpio71 = GPIO_LEVEL_HIGH,
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.gpio72 = GPIO_LEVEL_HIGH,
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};
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const struct pch_gpio_map mainboard_gpio_map = {
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.set1 = {
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.mode = &pch_gpio_set1_mode,
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.direction = &pch_gpio_set1_direction,
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.level = &pch_gpio_set1_level,
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.invert = &pch_gpio_set1_invert,
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},
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.set2 = {
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.mode = &pch_gpio_set2_mode,
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.direction = &pch_gpio_set2_direction,
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.level = &pch_gpio_set2_level,
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},
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.set3 = {
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.mode = &pch_gpio_set3_mode,
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.direction = &pch_gpio_set3_direction,
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.level = &pch_gpio_set3_level,
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},
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};
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#endif
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