1110495de9
SPI controllers in Intel and AMD bridges have a slightly different restriction on how long transactions they can handle. Change-Id: I3d149d4b7e7e9633482a153d5e380a86c553d871 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6163 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> |
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adesto.c | ||
amic.c | ||
eon.c | ||
gigadevice.c | ||
Kconfig | ||
macronix.c | ||
Makefile.inc | ||
spansion.c | ||
spi_flash.c | ||
spi_flash_internal.h | ||
sst.c | ||
stmicro.c | ||
winbond.c |