694 lines
17 KiB
C
694 lines
17 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <delay.h>
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#include <device/device.h>
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#include <device/resource.h>
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#include <device/pci.h>
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#include <stdint.h>
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#include <reg_script.h>
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#if IS_ENABLED(CONFIG_ARCH_X86)
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#include <cpu/x86/msr.h>
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#endif
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#define HAS_IOSF (IS_ENABLED(CONFIG_SOC_INTEL_BAYTRAIL) || \
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IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL))
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#if HAS_IOSF
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#include <soc/iosf.h> /* TODO: wrap in <soc/reg_script.h, remove #ifdef? */
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#endif
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#define POLL_DELAY 100 /* 100us */
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#if defined(__PRE_RAM__)
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#define EMPTY_DEV 0
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#else
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#define EMPTY_DEV NULL
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#endif
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static inline void reg_script_set_dev(struct reg_script_context *ctx,
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device_t dev)
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{
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ctx->dev = dev;
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ctx->res = NULL;
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}
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static inline void reg_script_set_step(struct reg_script_context *ctx,
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const struct reg_script *step)
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{
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ctx->step = step;
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}
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static inline const struct reg_script *
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reg_script_get_step(struct reg_script_context *ctx)
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{
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return ctx->step;
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}
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static struct resource *reg_script_get_resource(struct reg_script_context *ctx)
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{
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#if defined(__PRE_RAM__)
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return NULL;
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#else
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struct resource *res;
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const struct reg_script *step = reg_script_get_step(ctx);
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res = ctx->res;
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if (res != NULL && res->index == step->res_index)
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return res;
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res = find_resource(ctx->dev, step->res_index);
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ctx->res = res;
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return res;
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#endif
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}
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static uint32_t reg_script_read_pci(struct reg_script_context *ctx)
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{
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const struct reg_script *step = reg_script_get_step(ctx);
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switch (step->size) {
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case REG_SCRIPT_SIZE_8:
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return pci_read_config8(ctx->dev, step->reg);
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case REG_SCRIPT_SIZE_16:
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return pci_read_config16(ctx->dev, step->reg);
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case REG_SCRIPT_SIZE_32:
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return pci_read_config32(ctx->dev, step->reg);
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}
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return 0;
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}
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static void reg_script_write_pci(struct reg_script_context *ctx)
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{
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const struct reg_script *step = reg_script_get_step(ctx);
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switch (step->size) {
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case REG_SCRIPT_SIZE_8:
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pci_write_config8(ctx->dev, step->reg, step->value);
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break;
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case REG_SCRIPT_SIZE_16:
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pci_write_config16(ctx->dev, step->reg, step->value);
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break;
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case REG_SCRIPT_SIZE_32:
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pci_write_config32(ctx->dev, step->reg, step->value);
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break;
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}
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}
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static uint32_t reg_script_read_io(struct reg_script_context *ctx)
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{
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const struct reg_script *step = reg_script_get_step(ctx);
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switch (step->size) {
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case REG_SCRIPT_SIZE_8:
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return inb(step->reg);
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case REG_SCRIPT_SIZE_16:
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return inw(step->reg);
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case REG_SCRIPT_SIZE_32:
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return inl(step->reg);
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}
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return 0;
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}
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static void reg_script_write_io(struct reg_script_context *ctx)
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{
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const struct reg_script *step = reg_script_get_step(ctx);
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switch (step->size) {
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case REG_SCRIPT_SIZE_8:
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outb(step->value, step->reg);
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break;
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case REG_SCRIPT_SIZE_16:
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outw(step->value, step->reg);
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break;
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case REG_SCRIPT_SIZE_32:
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outl(step->value, step->reg);
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break;
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}
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}
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static uint32_t reg_script_read_mmio(struct reg_script_context *ctx)
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{
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const struct reg_script *step = reg_script_get_step(ctx);
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switch (step->size) {
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case REG_SCRIPT_SIZE_8:
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return read8((u8 *)step->reg);
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case REG_SCRIPT_SIZE_16:
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return read16((u16 *)step->reg);
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case REG_SCRIPT_SIZE_32:
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return read32((u32 *)step->reg);
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}
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return 0;
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}
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static void reg_script_write_mmio(struct reg_script_context *ctx)
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{
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const struct reg_script *step = reg_script_get_step(ctx);
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switch (step->size) {
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case REG_SCRIPT_SIZE_8:
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write8((u8 *)step->reg, step->value);
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break;
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case REG_SCRIPT_SIZE_16:
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write16((u16 *)step->reg, step->value);
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break;
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case REG_SCRIPT_SIZE_32:
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write32((u32 *)step->reg, step->value);
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break;
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}
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}
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static uint32_t reg_script_read_res(struct reg_script_context *ctx)
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{
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struct resource *res;
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uint32_t val = 0;
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const struct reg_script *step = reg_script_get_step(ctx);
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res = reg_script_get_resource(ctx);
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if (res == NULL)
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return val;
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if (res->flags & IORESOURCE_IO) {
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const struct reg_script io_step = {
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.size = step->size,
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.reg = res->base + step->reg,
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};
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reg_script_set_step(ctx, &io_step);
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val = reg_script_read_io(ctx);
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} else if (res->flags & IORESOURCE_MEM) {
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const struct reg_script mmio_step = {
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.size = step->size,
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.reg = res->base + step->reg,
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};
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reg_script_set_step(ctx, &mmio_step);
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val = reg_script_read_mmio(ctx);
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}
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reg_script_set_step(ctx, step);
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return val;
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}
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static void reg_script_write_res(struct reg_script_context *ctx)
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{
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struct resource *res;
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const struct reg_script *step = reg_script_get_step(ctx);
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res = reg_script_get_resource(ctx);
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if (res == NULL)
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return;
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if (res->flags & IORESOURCE_IO) {
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const struct reg_script io_step = {
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.size = step->size,
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.reg = res->base + step->reg,
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.value = step->value,
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};
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reg_script_set_step(ctx, &io_step);
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reg_script_write_io(ctx);
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} else if (res->flags & IORESOURCE_MEM) {
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const struct reg_script mmio_step = {
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.size = step->size,
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.reg = res->base + step->reg,
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.value = step->value,
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};
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reg_script_set_step(ctx, &mmio_step);
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reg_script_write_mmio(ctx);
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}
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reg_script_set_step(ctx, step);
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}
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#if HAS_IOSF
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static uint32_t reg_script_read_iosf(struct reg_script_context *ctx)
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{
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const struct reg_script *step = reg_script_get_step(ctx);
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switch (step->id) {
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case IOSF_PORT_AUNIT:
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return iosf_aunit_read(step->reg);
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case IOSF_PORT_CPU_BUS:
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return iosf_cpu_bus_read(step->reg);
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case IOSF_PORT_BUNIT:
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return iosf_bunit_read(step->reg);
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case IOSF_PORT_DUNIT_CH0:
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return iosf_dunit_ch0_read(step->reg);
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case IOSF_PORT_PMC:
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return iosf_punit_read(step->reg);
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case IOSF_PORT_USBPHY:
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return iosf_usbphy_read(step->reg);
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case IOSF_PORT_SEC:
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return iosf_sec_read(step->reg);
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case IOSF_PORT_0x45:
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return iosf_port45_read(step->reg);
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case IOSF_PORT_0x46:
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return iosf_port46_read(step->reg);
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case IOSF_PORT_0x47:
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return iosf_port47_read(step->reg);
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case IOSF_PORT_SCORE:
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return iosf_score_read(step->reg);
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case IOSF_PORT_0x55:
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return iosf_port55_read(step->reg);
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case IOSF_PORT_0x58:
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return iosf_port58_read(step->reg);
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case IOSF_PORT_0x59:
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return iosf_port59_read(step->reg);
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case IOSF_PORT_0x5a:
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return iosf_port5a_read(step->reg);
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case IOSF_PORT_USHPHY:
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return iosf_ushphy_read(step->reg);
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case IOSF_PORT_SCC:
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return iosf_scc_read(step->reg);
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case IOSF_PORT_LPSS:
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return iosf_lpss_read(step->reg);
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case IOSF_PORT_0xa2:
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return iosf_porta2_read(step->reg);
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case IOSF_PORT_CCU:
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return iosf_ccu_read(step->reg);
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case IOSF_PORT_SSUS:
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return iosf_ssus_read(step->reg);
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default:
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printk(BIOS_DEBUG, "No read support for IOSF port 0x%x.\n",
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step->id);
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break;
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}
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return 0;
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}
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static void reg_script_write_iosf(struct reg_script_context *ctx)
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{
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const struct reg_script *step = reg_script_get_step(ctx);
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switch (step->id) {
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case IOSF_PORT_AUNIT:
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iosf_aunit_write(step->reg, step->value);
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break;
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case IOSF_PORT_CPU_BUS:
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iosf_cpu_bus_write(step->reg, step->value);
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break;
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case IOSF_PORT_BUNIT:
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iosf_bunit_write(step->reg, step->value);
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break;
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case IOSF_PORT_DUNIT_CH0:
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iosf_dunit_write(step->reg, step->value);
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break;
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case IOSF_PORT_PMC:
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iosf_punit_write(step->reg, step->value);
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break;
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case IOSF_PORT_USBPHY:
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iosf_usbphy_write(step->reg, step->value);
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break;
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case IOSF_PORT_SEC:
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iosf_sec_write(step->reg, step->value);
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break;
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case IOSF_PORT_0x45:
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iosf_port45_write(step->reg, step->value);
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break;
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case IOSF_PORT_0x46:
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iosf_port46_write(step->reg, step->value);
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break;
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case IOSF_PORT_0x47:
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iosf_port47_write(step->reg, step->value);
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break;
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case IOSF_PORT_SCORE:
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iosf_score_write(step->reg, step->value);
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break;
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case IOSF_PORT_0x55:
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iosf_port55_write(step->reg, step->value);
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break;
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case IOSF_PORT_0x58:
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iosf_port58_write(step->reg, step->value);
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break;
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case IOSF_PORT_0x59:
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iosf_port59_write(step->reg, step->value);
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break;
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case IOSF_PORT_0x5a:
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iosf_port5a_write(step->reg, step->value);
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break;
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case IOSF_PORT_USHPHY:
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iosf_ushphy_write(step->reg, step->value);
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break;
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case IOSF_PORT_SCC:
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iosf_scc_write(step->reg, step->value);
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break;
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case IOSF_PORT_LPSS:
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iosf_lpss_write(step->reg, step->value);
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break;
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case IOSF_PORT_0xa2:
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iosf_porta2_write(step->reg, step->value);
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break;
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case IOSF_PORT_CCU:
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iosf_ccu_write(step->reg, step->value);
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break;
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case IOSF_PORT_SSUS:
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iosf_ssus_write(step->reg, step->value);
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break;
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default:
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printk(BIOS_DEBUG, "No write support for IOSF port 0x%x.\n",
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step->id);
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break;
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}
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}
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#endif /* HAS_IOSF */
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static uint64_t reg_script_read_msr(struct reg_script_context *ctx)
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{
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#if IS_ENABLED(CONFIG_ARCH_X86)
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const struct reg_script *step = reg_script_get_step(ctx);
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msr_t msr = rdmsr(step->reg);
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uint64_t value = msr.hi;
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value <<= 32;
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value |= msr.lo;
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return value;
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#endif
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}
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static void reg_script_write_msr(struct reg_script_context *ctx)
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{
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#if IS_ENABLED(CONFIG_ARCH_X86)
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const struct reg_script *step = reg_script_get_step(ctx);
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msr_t msr;
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msr.hi = step->value >> 32;
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msr.lo = step->value & 0xffffffff;
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wrmsr(step->reg, msr);
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#endif
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}
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/* Locate the structure containing the platform specific bus access routines */
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static const struct reg_script_bus_entry
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*find_bus(const struct reg_script *step)
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{
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extern const struct reg_script_bus_entry *_rsbe_init_begin[];
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extern const struct reg_script_bus_entry *_ersbe_init_begin[];
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const struct reg_script_bus_entry * const *bus;
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size_t table_entries;
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size_t i;
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/* Locate the platform specific bus */
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bus = _rsbe_init_begin;
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table_entries = &_ersbe_init_begin[0] - &_rsbe_init_begin[0];
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for (i = 0; i < table_entries; i++) {
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if (bus[i]->type == step->type)
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return bus[i];
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}
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/* Bus not found */
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return NULL;
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}
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static void reg_script_display(struct reg_script_context *ctx,
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const struct reg_script *step, const char *arrow, uint64_t value)
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{
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/* Display the register address and data */
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if (ctx->display_prefix != NULL)
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printk(BIOS_INFO, "%s: ", ctx->display_prefix);
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if (ctx->display_features & REG_SCRIPT_DISPLAY_REGISTER)
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printk(BIOS_INFO, "0x%08x %s ", step->reg, arrow);
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if (ctx->display_features & REG_SCRIPT_DISPLAY_VALUE)
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switch (step->size) {
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case REG_SCRIPT_SIZE_8:
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printk(BIOS_INFO, "0x%02x\n", (uint8_t)value);
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break;
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case REG_SCRIPT_SIZE_16:
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printk(BIOS_INFO, "0x%04x\n", (int16_t)value);
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break;
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case REG_SCRIPT_SIZE_32:
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printk(BIOS_INFO, "0x%08x\n", (uint32_t)value);
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break;
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default:
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printk(BIOS_INFO, "0x%016llx\n", value);
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break;
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}
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}
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static uint64_t reg_script_read(struct reg_script_context *ctx)
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{
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const struct reg_script *step = reg_script_get_step(ctx);
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uint64_t value = 0;
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switch (step->type) {
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case REG_SCRIPT_TYPE_PCI:
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ctx->display_prefix = "PCI";
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value = reg_script_read_pci(ctx);
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break;
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case REG_SCRIPT_TYPE_IO:
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ctx->display_prefix = "IO";
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value = reg_script_read_io(ctx);
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break;
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case REG_SCRIPT_TYPE_MMIO:
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ctx->display_prefix = "MMIO";
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value = reg_script_read_mmio(ctx);
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break;
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case REG_SCRIPT_TYPE_RES:
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ctx->display_prefix = "RES";
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value = reg_script_read_res(ctx);
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break;
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case REG_SCRIPT_TYPE_MSR:
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ctx->display_prefix = "MSR";
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value = reg_script_read_msr(ctx);
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break;
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#if HAS_IOSF
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case REG_SCRIPT_TYPE_IOSF:
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ctx->display_prefix = "IOSF";
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value = reg_script_read_iosf(ctx);
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break;
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#endif /* HAS_IOSF */
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default:
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{
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const struct reg_script_bus_entry *bus;
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/* Read from the platform specific bus */
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bus = find_bus(step);
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if (bus != NULL) {
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value = bus->reg_script_read(ctx);
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break;
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}
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}
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printk(BIOS_ERR,
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"Unsupported read type (0x%x) for this device!\n",
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step->type);
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return 0;
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}
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/* Display the register address and data */
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if (ctx->display_features)
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reg_script_display(ctx, step, "-->", value);
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return value;
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}
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static void reg_script_write(struct reg_script_context *ctx)
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{
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const struct reg_script *step = reg_script_get_step(ctx);
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switch (step->type) {
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case REG_SCRIPT_TYPE_PCI:
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ctx->display_prefix = "PCI";
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reg_script_write_pci(ctx);
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break;
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case REG_SCRIPT_TYPE_IO:
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ctx->display_prefix = "IO";
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reg_script_write_io(ctx);
|
|
break;
|
|
case REG_SCRIPT_TYPE_MMIO:
|
|
ctx->display_prefix = "MMIO";
|
|
reg_script_write_mmio(ctx);
|
|
break;
|
|
case REG_SCRIPT_TYPE_RES:
|
|
ctx->display_prefix = "RES";
|
|
reg_script_write_res(ctx);
|
|
break;
|
|
case REG_SCRIPT_TYPE_MSR:
|
|
ctx->display_prefix = "MSR";
|
|
reg_script_write_msr(ctx);
|
|
break;
|
|
#if HAS_IOSF
|
|
case REG_SCRIPT_TYPE_IOSF:
|
|
ctx->display_prefix = "IOSF";
|
|
reg_script_write_iosf(ctx);
|
|
break;
|
|
#endif /* HAS_IOSF */
|
|
default:
|
|
{
|
|
const struct reg_script_bus_entry *bus;
|
|
|
|
/* Write to the platform specific bus */
|
|
bus = find_bus(step);
|
|
if (bus != NULL) {
|
|
bus->reg_script_write(ctx);
|
|
break;
|
|
}
|
|
}
|
|
printk(BIOS_ERR,
|
|
"Unsupported write type (0x%x) for this device!\n",
|
|
step->type);
|
|
return;
|
|
}
|
|
|
|
/* Display the register address and data */
|
|
if (ctx->display_features)
|
|
reg_script_display(ctx, step, "<--", step->value);
|
|
}
|
|
|
|
static void reg_script_rmw(struct reg_script_context *ctx)
|
|
{
|
|
uint64_t value;
|
|
const struct reg_script *step = reg_script_get_step(ctx);
|
|
struct reg_script write_step = *step;
|
|
|
|
value = reg_script_read(ctx);
|
|
value &= step->mask;
|
|
value |= step->value;
|
|
write_step.value = value;
|
|
reg_script_set_step(ctx, &write_step);
|
|
reg_script_write(ctx);
|
|
reg_script_set_step(ctx, step);
|
|
}
|
|
|
|
static void reg_script_rxw(struct reg_script_context *ctx)
|
|
{
|
|
uint64_t value;
|
|
const struct reg_script *step = reg_script_get_step(ctx);
|
|
struct reg_script write_step = *step;
|
|
|
|
/*
|
|
* XOR logic table
|
|
* Input XOR Value
|
|
* 0 0 0
|
|
* 0 1 1
|
|
* 1 0 1
|
|
* 1 1 0
|
|
*
|
|
* Supported operations
|
|
*
|
|
* Input Mask Temp XOR Value Operation
|
|
* 0 0 0 0 0 Clear bit
|
|
* 1 0 0 0 0
|
|
* 0 0 0 1 1 Set bit
|
|
* 1 0 0 1 1
|
|
* 0 1 0 0 0 Preserve bit
|
|
* 1 1 1 0 1
|
|
* 0 1 0 1 1 Toggle bit
|
|
* 1 1 1 1 0
|
|
*/
|
|
value = reg_script_read(ctx);
|
|
value &= step->mask;
|
|
value ^= step->value;
|
|
write_step.value = value;
|
|
reg_script_set_step(ctx, &write_step);
|
|
reg_script_write(ctx);
|
|
reg_script_set_step(ctx, step);
|
|
}
|
|
|
|
/* In order to easily chain scripts together handle the REG_SCRIPT_COMMAND_NEXT
|
|
* as recursive call with a new context that has the same dev and resource
|
|
* as the previous one. That will run to completion and then move on to the
|
|
* next step of the previous context. */
|
|
static void reg_script_run_next(struct reg_script_context *ctx,
|
|
const struct reg_script *step);
|
|
|
|
|
|
static void reg_script_run_step(struct reg_script_context *ctx,
|
|
const struct reg_script *step)
|
|
{
|
|
uint64_t value = 0, try;
|
|
|
|
ctx->display_features = ctx->display_state;
|
|
ctx->display_prefix = NULL;
|
|
switch (step->command) {
|
|
case REG_SCRIPT_COMMAND_READ:
|
|
(void)reg_script_read(ctx);
|
|
break;
|
|
case REG_SCRIPT_COMMAND_WRITE:
|
|
reg_script_write(ctx);
|
|
break;
|
|
case REG_SCRIPT_COMMAND_RMW:
|
|
reg_script_rmw(ctx);
|
|
break;
|
|
case REG_SCRIPT_COMMAND_RXW:
|
|
reg_script_rxw(ctx);
|
|
break;
|
|
case REG_SCRIPT_COMMAND_POLL:
|
|
for (try = 0; try < step->timeout; try += POLL_DELAY) {
|
|
value = reg_script_read(ctx) & step->mask;
|
|
if (value == step->value)
|
|
break;
|
|
udelay(POLL_DELAY);
|
|
}
|
|
if (try >= step->timeout)
|
|
printk(BIOS_WARNING, "%s: POLL timeout waiting for "
|
|
"0x%x to be 0x%lx, got 0x%lx\n", __func__,
|
|
step->reg, (unsigned long)step->value,
|
|
(unsigned long)value);
|
|
break;
|
|
case REG_SCRIPT_COMMAND_SET_DEV:
|
|
reg_script_set_dev(ctx, step->dev);
|
|
break;
|
|
case REG_SCRIPT_COMMAND_NEXT:
|
|
reg_script_run_next(ctx, step->next);
|
|
break;
|
|
case REG_SCRIPT_COMMAND_DISPLAY:
|
|
ctx->display_state = step->value;
|
|
break;
|
|
|
|
default:
|
|
printk(BIOS_WARNING, "Invalid command: %08x\n",
|
|
step->command);
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void reg_script_run_with_context(struct reg_script_context *ctx)
|
|
{
|
|
while (1) {
|
|
const struct reg_script *step = reg_script_get_step(ctx);
|
|
|
|
if (step->command == REG_SCRIPT_COMMAND_END)
|
|
break;
|
|
|
|
reg_script_run_step(ctx, step);
|
|
reg_script_set_step(ctx, step + 1);
|
|
}
|
|
}
|
|
|
|
static void reg_script_run_next(struct reg_script_context *prev_ctx,
|
|
const struct reg_script *step)
|
|
{
|
|
struct reg_script_context ctx;
|
|
|
|
/* Use prev context as a basis but start at a new step. */
|
|
ctx = *prev_ctx;
|
|
reg_script_set_step(&ctx, step);
|
|
reg_script_run_with_context(&ctx);
|
|
}
|
|
|
|
void reg_script_run_on_dev(device_t dev, const struct reg_script *step)
|
|
{
|
|
struct reg_script_context ctx;
|
|
|
|
ctx.display_state = REG_SCRIPT_DISPLAY_NOTHING;
|
|
reg_script_set_dev(&ctx, dev);
|
|
reg_script_set_step(&ctx, step);
|
|
reg_script_run_with_context(&ctx);
|
|
}
|
|
|
|
void reg_script_run(const struct reg_script *step)
|
|
{
|
|
reg_script_run_on_dev(EMPTY_DEV, step);
|
|
}
|