a73b93157f
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
107 lines
5.2 KiB
Text
107 lines
5.2 KiB
Text
#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2011 Advanced Micro Devices, Inc.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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chip northbridge/amd/agesa/family14/root_complex
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device cpu_cluster 0 on
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chip cpu/amd/agesa/family14
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device lapic 0 on end
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end
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end
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device domain 0 on
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subsystemid 0x1022 0x1510 inherit
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chip northbridge/amd/agesa/family14 # CPU side of HT root complex
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# device pci 18.0 on # northbridge
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chip northbridge/amd/agesa/family14 # PCI side of HT root complex
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device pci 0.0 on end # Root Complex
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device pci 1.0 on end # Internal Graphics P2P bridge 0x9804
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device pci 1.1 on end # Internal HDMI Audio
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device pci 4.0 on end # PCIE P2P bridge 0x9604
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device pci 5.0 on end # PCIE P2P bridge 0x9605
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device pci 6.0 on end # PCIE P2P bridge 0x9606
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device pci 7.0 on end # PCIE P2P bridge 0x9607
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device pci 8.0 on end # NB/SB Link P2P bridge
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end # agesa northbridge
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chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus
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device pci 11.0 on end # SATA
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device pci 12.0 on end # USB
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device pci 12.1 on end # USB
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device pci 12.2 on end # USB
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device pci 13.0 on end # USB
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device pci 13.1 on end # USB
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device pci 13.2 on end # USB
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device pci 14.0 on # SM
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## chip drivers/generic/generic #dimm 0-0-0
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## device i2c 50 on end
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## end
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## chip drivers/generic/generic #dimm 0-0-1
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## device i2c 51 on end
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## end
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end # SM
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device pci 14.1 on end # IDE 0x439c
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device pci 14.2 on end # HDA 0x4383
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device pci 14.3 on # LPC 0x439d
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chip superio/fintek/f81865f
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device pnp 4e.0 off # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 4e.3 off end # Parallel Port
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device pnp 4e.4 off end # Hardware Monitor
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device pnp 4e.5 on # Keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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end
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device pnp 4e.6 off end # GPIO
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device pnp 4e.a off end # PME
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device pnp 4e.10 on # COM1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 4e.11 off # COM2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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end # f81865f
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end #LPC
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device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
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device pci 14.5 on end # USB 2
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device pci 15.0 off end # PCIe PortA
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device pci 15.1 off end # PCIe PortB
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device pci 15.2 off end # PCIe PortC
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device pci 15.3 off end # PCIe PortD
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device pci 16.0 off end # OHCI USB3
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device pci 16.2 off end # EHCI USB3
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register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow)
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register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
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end #southbridge/amd/cimx/sb800
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# end # device pci 18.0
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# These seem unnecessary
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device pci 18.1 on end
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device pci 18.2 on end
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device pci 18.3 on end
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device pci 18.4 on end
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device pci 18.5 on end
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register "spdAddrLookup" = "
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{
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{ {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
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{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
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}"
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end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex
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end #domain
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end #northbridge/amd/agesa/family14/root_complex
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