1156b35a23
Change-Id: Ib3aafcc586b1631a75f214cfd19706108ad8ca93 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29285 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
145 lines
4.5 KiB
C
145 lines
4.5 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/smp/mpspec.h>
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#include <device/pci.h>
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#include <arch/io.h>
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#include <arch/ioapic.h>
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#include <string.h>
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#include <stdint.h>
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#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
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u8 intr_data[] = {
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[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
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[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
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[0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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0x10,0x11,0x12,0x13
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};
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static void *smp_write_config_table(void *v)
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{
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struct mp_config_table *mc;
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int bus_isa;
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/*
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* By the time this function gets called, the IOAPIC registers
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* have been written so they can be read to get the correct
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* APIC ID and Version
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*/
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u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
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u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
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mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
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mptable_init(mc, LOCAL_APIC_ADDR);
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memcpy(mc->mpc_oem, "AMD ", 8);
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smp_write_processors(mc);
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mptable_write_buses(mc, NULL, &bus_isa);
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/* I/O APICs: APIC ID Version State Address */
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smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
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u8 byte;
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for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
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outb(byte | 0x80, 0xC00);
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outb(intr_data[byte], 0xC01);
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}
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/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
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#define IO_LOCAL_INT(type, intr, apicid, pin) \
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smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
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mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
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/* PCI interrupts are level triggered, and are
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* associated with a specific bus/device/function tuple.
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*/
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#define PCI_INT(bus, dev, fn, pin) \
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
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/* APU Internal Graphic Device*/
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PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
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PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
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//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
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PCI_INT(0x0, 0x14, 0x0, 0x10);
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/* Southbridge HD Audio: */
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PCI_INT(0x0, 0x14, 0x2, 0x12);
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PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
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PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
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PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
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PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
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PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
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PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
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/* sata */
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PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
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/* on board NIC & Slot PCIE. */
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/* PCI slots */
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struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
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if (dev && dev->enabled) {
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u8 bus_pci = dev->link_list->secondary;
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/* PCI_SLOT 0. */
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PCI_INT(bus_pci, 0x5, 0x0, 0x14);
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PCI_INT(bus_pci, 0x5, 0x1, 0x15);
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PCI_INT(bus_pci, 0x5, 0x2, 0x16);
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PCI_INT(bus_pci, 0x5, 0x3, 0x17);
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/* PCI_SLOT 1. */
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PCI_INT(bus_pci, 0x6, 0x0, 0x15);
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PCI_INT(bus_pci, 0x6, 0x1, 0x16);
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PCI_INT(bus_pci, 0x6, 0x2, 0x17);
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PCI_INT(bus_pci, 0x6, 0x3, 0x14);
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/* PCI_SLOT 2. */
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PCI_INT(bus_pci, 0x7, 0x0, 0x16);
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PCI_INT(bus_pci, 0x7, 0x1, 0x17);
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PCI_INT(bus_pci, 0x7, 0x2, 0x14);
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PCI_INT(bus_pci, 0x7, 0x3, 0x15);
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}
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/* PCIe PortA */
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PCI_INT(0x0, 0x15, 0x0, 0x10);
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/* PCIe PortB */
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PCI_INT(0x0, 0x15, 0x1, 0x11);
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/* PCIe PortC */
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PCI_INT(0x0, 0x15, 0x2, 0x12);
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/* PCIe PortD */
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PCI_INT(0x0, 0x15, 0x3, 0x13);
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/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
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IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
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IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
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/* There is no extension information... */
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/* Compute the checksums */
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return mptable_finalize(mc);
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}
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unsigned long write_smp_table(unsigned long addr)
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{
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void *v;
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v = smp_write_floating_table(addr, 0);
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return (unsigned long)smp_write_config_table(v);
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}
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