4ad1446b83
Also remove some unnedded includes. Change-Id: I036208a111d009620d8354fa9c97688eb4e872ad Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
139 lines
3.7 KiB
C
139 lines
3.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Alec Ari <neotheuser@ymail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <arch/io.h>
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#include <device/pci_def.h>
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#include <southbridge/amd/sb700/sb700.h>
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#include <southbridge/amd/sb700/smbus.h>
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#include <southbridge/amd/rs780/rs780.h>
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void set_pcie_dereset(void)
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{
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u8 byte;
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u16 word;
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struct device *sm_dev;
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/* set 0 to bit1 :disable GPM9 as SLP_S2 output */
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/* set 0 to bit2 :disable GPM8 as AZ_RST output */
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byte = pm_ioread(0x8d);
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byte &= ~((1 << 1) | (1 << 2));
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pm_iowrite(0x8d, byte);
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/* set the GPM8 and GPM9 output enable and the value to 1 */
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byte = pm_ioread(0x94);
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byte &= ~((1 << 2) | (1 << 3));
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byte |= ((1 << 0) | (1 << 1));
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pm_iowrite(0x94, byte);
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/* set the GPIO65 output enable and the value is 1 */
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sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
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word = pci_read_config16(sm_dev, 0x7e);
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word |= (1 << 0);
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word &= ~(1 << 4);
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pci_write_config16(sm_dev, 0x7e, word);
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}
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void set_pcie_reset(void)
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{
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u8 byte;
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u16 word;
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struct device *sm_dev;
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/* set 0 to bit1 :disable GPM9 as SLP_S2 output */
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/* set 0 to bit2 :disable GPM8 as AZ_RST output */
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byte = pm_ioread(0x8d);
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byte &= ~((1 << 1) | (1 << 2));
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pm_iowrite(0x8d, byte);
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/* set the GPM8 and GPM9 output enable and the value to 0 */
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byte = pm_ioread(0x94);
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byte &= ~((1 << 2) | (1 << 3));
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byte &= ~((1 << 0) | (1 << 1));
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pm_iowrite(0x94, byte);
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/* set the GPIO65 output enable and the value is 0 */
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sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
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word = pci_read_config16(sm_dev, 0x7e);
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word &= ~(1 << 0);
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word &= ~(1 << 4);
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pci_write_config16(sm_dev, 0x7e, word);
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}
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/*
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* dev3 does not exist on ma785gm
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*/
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int is_dev3_present(void)
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{
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return 0;
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}
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/*
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* set gpio40 gfx
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*/
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static void set_gpio40_gfx(void)
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{
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u8 byte;
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// u16 word;
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u32 dword;
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struct device *sm_dev;
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/* disable the GPIO40 as CLKREQ2# function */
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byte = pm_ioread(0xd3);
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byte &= ~(1 << 7);
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pm_iowrite(0xd3, byte);
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/* disable the GPIO40 as CLKREQ3# function */
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byte = pm_ioread(0xd4);
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byte &= ~(1 << 0);
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pm_iowrite(0xd4, byte);
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/* enable pull up for GPIO68 */
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byte = pm2_ioread(0xf1);
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byte &= ~(1 << 4);
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pm2_iowrite(0xf1, byte);
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/* access the smbus extended register */
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sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
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/* set the gfx to 1x16 lanes */
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printk(BIOS_INFO, "Dev3 is not present. GFX Configuration is One x16 slot\n");
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/* when the gpio40 is configured as GPIO, this will enable the output */
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pci_write_config32(sm_dev, 0xf8, 0x4);
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dword = pci_read_config32(sm_dev, 0xfc);
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dword &= ~(1 << 10);
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/* When the gpio40 is configured as GPIO, this will represent the output value*/
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/* 1 :enable two x8 , 0 : master slot enable only */
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dword &= ~(1 << 26);
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pci_write_config32(sm_dev, 0xfc, dword);
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}
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/*************************************************
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* enable the dedicated function in ma785gm board.
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* This function called early than rs780_enable.
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*************************************************/
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static void mainboard_enable(struct device *dev)
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{
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printk(BIOS_INFO, "Mainboard MA785GM-US2H Enable. dev=0x%p\n", dev);
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set_pcie_dereset();
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/* get_ide_dma66(); */
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set_gpio40_gfx();
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}
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struct chip_operations mainboard_ops = {
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.enable_dev = mainboard_enable,
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};
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