94aed8d615
Add config option to enable eSPI TEST=Boot to OS Change-Id: Ib4634690fe4fdb902fc0bc074a3b66b91921ddd5 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/22320 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Hannah Williams <hannah.williams@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
399 lines
9.1 KiB
Text
399 lines
9.1 KiB
Text
config SOC_INTEL_APOLLOLAKE
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bool
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help
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Intel Apollolake support
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config SOC_INTEL_GLK
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bool
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default n
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select SOC_INTEL_APOLLOLAKE
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select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
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select SOC_INTEL_COMMON_BLOCK_SGX
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help
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Intel GLK support
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if SOC_INTEL_APOLLOLAKE
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config CPU_SPECIFIC_OPTIONS
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def_bool y
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select ACPI_INTEL_HARDWARE_SLEEP_VALUES
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select ARCH_BOOTBLOCK_X86_32
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select ARCH_RAMSTAGE_X86_32
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select ARCH_ROMSTAGE_X86_32
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select ARCH_VERSTAGE_X86_32
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select BOOTBLOCK_CONSOLE
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select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
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select BOOT_DEVICE_SUPPORTS_WRITES
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# CPU specific options
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select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
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select IOAPIC
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select PCR_COMMON_IOSF_1_0
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select SMP
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select SSE2
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select SUPPORT_CPU_UCODE_IN_CBFS
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# Audio options
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select ACPI_NHLT
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select SOC_INTEL_COMMON_NHLT
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# Misc options
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select C_ENVIRONMENT_BOOTBLOCK
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select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE
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select COLLECT_TIMESTAMPS
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select COMMON_FADT
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select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS
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select GENERIC_GPIO_LIB
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select HAVE_INTEL_FIRMWARE
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select HAVE_SMI_HANDLER
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select MRC_SETTINGS_PROTECT
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select NO_FIXED_XIP_ROM_SIZE
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select NO_XIP_EARLY_STAGES
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select PARALLEL_MP
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select PARALLEL_MP_AP_WORK
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select PCIEXP_ASPM
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select PCIEXP_COMMON_CLOCK
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select PCIEXP_CLK_PM
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select PCIEXP_L1_SUB_STATE
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select PCIEX_LENGTH_256MB
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select POSTCAR_CONSOLE
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select POSTCAR_STAGE
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select REG_SCRIPT
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select RELOCATABLE_RAMSTAGE # Build fails if this is not selected
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select RTC
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select SMM_TSEG
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select SA_ENABLE_IMR
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select SOC_INTEL_COMMON
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select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
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select SOC_INTEL_COMMON_BLOCK
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select SOC_INTEL_COMMON_BLOCK_ACPI
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select SOC_INTEL_COMMON_BLOCK_CPU
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select SOC_INTEL_COMMON_BLOCK_DSP
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select SOC_INTEL_COMMON_BLOCK_FAST_SPI
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select SOC_INTEL_COMMON_BLOCK_GPIO
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select SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES
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select SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG
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select SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY
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select SOC_INTEL_COMMON_BLOCK_GRAPHICS
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select SOC_INTEL_COMMON_BLOCK_ITSS
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select SOC_INTEL_COMMON_BLOCK_I2C
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select SOC_INTEL_COMMON_BLOCK_LPC
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select SOC_INTEL_COMMON_BLOCK_LPSS
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select SOC_INTEL_COMMON_BLOCK_PCR
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select SOC_INTEL_COMMON_BLOCK_P2SB
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select SOC_INTEL_COMMON_BLOCK_PMC
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select SOC_INTEL_COMMON_BLOCK_SRAM
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select SOC_INTEL_COMMON_BLOCK_RTC
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select SOC_INTEL_COMMON_BLOCK_SA
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select SOC_INTEL_COMMON_BLOCK_SCS
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select SOC_INTEL_COMMON_BLOCK_TIMER
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select SOC_INTEL_COMMON_BLOCK_UART
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select SOC_INTEL_COMMON_BLOCK_XDCI
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select SOC_INTEL_COMMON_BLOCK_XHCI
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select SOC_INTEL_COMMON_BLOCK_SMM
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select SOC_INTEL_COMMON_BLOCK_SPI
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select SOC_INTEL_COMMON_SPI_FLASH_PROTECT
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select UDELAY_TSC
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select TSC_CONSTANT_RATE
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select TSC_MONOTONIC_TIMER
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select HAVE_MONOTONIC_TIMER
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select PLATFORM_USES_FSP2_0
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select HAVE_HARD_RESET
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select SOC_INTEL_COMMON
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select SOC_INTEL_COMMON_GFX_OPREGION
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select SOC_INTEL_COMMON_BLOCK
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select SOC_INTEL_COMMON_BLOCK_CSE
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select INTEL_GMA_ADD_VBT_DATA_FILE if RUN_FSP_GOP
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select HAVE_FSP_GOP
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config CHROMEOS
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select CHROMEOS_RAMOOPS_DYNAMIC
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config VBOOT
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select VBOOT_SEPARATE_VERSTAGE
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select VBOOT_OPROM_MATTERS
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select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT
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select VBOOT_STARTS_IN_BOOTBLOCK
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select VBOOT_VBNV_CMOS
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select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
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config TPM_ON_FAST_SPI
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bool
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default n
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select LPC_TPM
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help
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TPM part is conntected on Fast SPI interface, but the LPC MMIO
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TPM transactions are decoded and serialized over the SPI interface.
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config SOC_INTEL_COMMON_RESET
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bool
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default y
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config PCR_BASE_ADDRESS
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hex
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default 0xd0000000
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help
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This option allows you to select MMIO Base Address of sideband bus.
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config DCACHE_RAM_BASE
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hex
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default 0xfef00000
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config DCACHE_RAM_SIZE
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hex
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default 0xc0000
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help
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The size of the cache-as-ram region required during bootblock
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and/or romstage.
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config DCACHE_BSP_STACK_SIZE
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hex
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default 0x4000
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help
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The amount of anticipated stack usage in CAR by bootblock and
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other stages.
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config CPU_ADDR_BITS
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int
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default 36
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config SOC_INTEL_COMMON_LPSS_CLOCK_MHZ
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int
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default 133
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config CONSOLE_UART_BASE_ADDRESS
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depends on CONSOLE_SERIAL
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hex
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default 0xde000000
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config SOC_UART_DEBUG
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bool "Enable SoC UART debug port selected by UART_FOR_CONSOLE."
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default n
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select CONSOLE_SERIAL
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select DRIVERS_UART
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select DRIVERS_UART_8250MEM_32
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select NO_UART_ON_SUPERIO
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# 32KiB bootblock is all that is mapped in by the CSE at top of 4GiB.
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config C_ENV_BOOTBLOCK_SIZE
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hex
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default 0x8000
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# This SoC does not map SPI flash like many previous SoC. Therefore we provide
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# a custom media driver that facilitates mapping
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config X86_TOP4G_BOOTMEDIA_MAP
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bool
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default n
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config ROMSTAGE_ADDR
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hex
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default 0xfef20000
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help
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The base address (in CAR) where romstage should be linked
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config VERSTAGE_ADDR
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hex
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default 0xfef40000
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help
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The base address (in CAR) where verstage should be linked
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config CACHE_MRC_SETTINGS
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bool
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default y
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config MRC_SETTINGS_VARIABLE_DATA
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bool
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default y
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config FSP_M_ADDR
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hex
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default 0xfef40000
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help
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The address FSP-M will be relocated to during build time
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config NEED_LBP2
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bool "Write contents for logical boot partition 2."
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default n
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help
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Write the contents from a file into the logical boot partition 2
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region defined by LBP2_FMAP_NAME.
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config LBP2_FMAP_NAME
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string "Name of FMAP region to put logical boot partition 2"
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depends on NEED_LBP2
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default "SIGN_CSE"
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help
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Name of FMAP region to write logical boot partition 2 data.
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config LBP2_FILE_NAME
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string "Path of file to write to logical boot partition 2 region"
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depends on NEED_LBP2
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default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/lbp2.bin"
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help
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Name of file to store in the logical boot partition 2 region.
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config NEED_IFWI
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bool "Write content into IFWI region"
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default n
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help
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Write the content from a file into IFWI region defined by
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IFWI_FMAP_NAME.
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config IFWI_FMAP_NAME
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string "Name of FMAP region to pull IFWI into"
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depends on NEED_IFWI
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default "IFWI"
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help
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Name of FMAP region to write IFWI.
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config IFWI_FILE_NAME
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string "Path of file to write to IFWI region"
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depends on NEED_IFWI
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default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/ifwi.bin"
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help
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Name of file to store in the IFWI region.
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config HEAP_SIZE
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hex
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default 0x8000
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config NHLT_DMIC_1CH_16B
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bool
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depends on ACPI_NHLT
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default n
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help
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Include DSP firmware settings for 1 channel 16B DMIC array.
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config NHLT_DMIC_2CH_16B
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bool
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depends on ACPI_NHLT
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default n
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help
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Include DSP firmware settings for 2 channel 16B DMIC array.
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config NHLT_DMIC_4CH_16B
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bool
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depends on ACPI_NHLT
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default n
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help
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Include DSP firmware settings for 4 channel 16B DMIC array.
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config NHLT_MAX98357
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bool
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depends on ACPI_NHLT
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default n
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help
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Include DSP firmware settings for headset codec.
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config NHLT_DA7219
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bool
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depends on ACPI_NHLT
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default n
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help
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Include DSP firmware settings for headset codec.
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choice
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prompt "Cache-as-ram implementation"
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default CAR_CQOS if !SOC_INTEL_GLK
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default CAR_NEM
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help
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This option allows you to select how cache-as-ram (CAR) is set up.
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config CAR_NEM
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bool "Non-evict mode"
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select SOC_INTEL_COMMON_BLOCK_CAR
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select INTEL_CAR_NEM
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help
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Traditionally, CAR is set up by using Non-Evict mode. This method
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does not allow CAR and cache to co-exist, because cache fills are
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block in NEM mode.
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config CAR_CQOS
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bool "Cache Quality of Service"
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select SOC_INTEL_COMMON_BLOCK_CAR
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select INTEL_CAR_CQOS
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help
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Cache Quality of Service allows more fine-grained control of cache
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usage. As result, it is possible to set up portion of L2 cache for
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CAR and use remainder for actual caching.
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config USE_APOLLOLAKE_FSP_CAR
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bool "Use FSP CAR"
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select FSP_CAR
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help
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Use FSP APIs to initialize & tear down the Cache-As-Ram.
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endchoice
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choice
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prompt "MPINIT code implementation"
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default NO_COMMON_MPINIT if SOC_INTEL_APOLLOLAKE
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default COMMON_MPINIT
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help
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This option allows you to select MP Init Code path either
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from Intel Common Code implementation, or from SOC files.
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config NO_COMMON_MPINIT
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bool "Not using Common MP Init code"
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help
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Common code MP Init path is not used.
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config COMMON_MPINIT
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bool "Using Common MP Init code"
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select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
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help
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Common code MP Init path is used.
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endchoice
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#
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# Each bit in QOS mask controls this many bytes. This is calculated as:
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# (CACHE_WAYS / CACHE_BITS_PER_MASK) * CACHE_LINE_SIZE * CACHE_SETS
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#
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config CACHE_QOS_SIZE_PER_BIT
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hex
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default 0x20000 # 128 KB
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config L2_CACHE_SIZE
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hex
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default 0x100000
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config SPI_FLASH_INCLUDE_ALL_DRIVERS
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bool
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default n
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config SMM_RESERVED_SIZE
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hex
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default 0x100000
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config IFD_CHIPSET
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string
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default "aplk"
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config CPU_BCLK_MHZ
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int
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default 100
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config APL_SKIP_SET_POWER_LIMITS
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bool
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default n
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help
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Some Apollo Lake mainboards do not need the Running Average Power
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Limits (RAPL) algorithm for a constant power management.
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Set this config option to skip the RAPL configuration.
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# M and N divisor values for clock frequency configuration.
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# These values get us a 1.836 MHz clock (ideally we want 1.843 MHz)
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config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
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hex
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default 0x25a
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config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
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hex
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default 0x7fff
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config SOC_ESPI
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bool
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default n
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help
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Use eSPI bus instead of LPC
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endif
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