83a1dd850b
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5306 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
46 lines
1.6 KiB
C
46 lines
1.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef SOUTHBRIDGE_AMD_CS5530_CS5530_H
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#define SOUTHBRIDGE_AMD_CS5530_CS5530_H
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#if !defined(__PRE_RAM__)
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#include "chip.h"
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void cs5530_enable(device_t dev);
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#endif
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#define DECODE_CONTROL_REG2 0x5b /* F0 index 0x5b */
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#define ROM_AT_LOGIC_CONTROL_REG 0x52 /* F0 index 0x52 */
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#define LOWER_ROM_ADDRESS_RANGE (1 << 0)
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#define ROM_WRITE_ENABLE (1 << 1)
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#define UPPER_ROM_ADDRESS_RANGE (1 << 2)
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#define BIOS_ROM_POSITIVE_DECODE (1 << 5)
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/* Selects PCI positive decoding for accesses to the configured ROM space. */
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#define BIOS_ROM_POSITIVE_DECODE (1 << 5)
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/* Primary IDE Controller Positive Decode (i.e., enable it). */
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#define PRIMARY_IDE_ENABLE (1 << 3)
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/* Secondary IDE Controller Positive Decode (i.e., enable it). */
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#define SECONDARY_IDE_ENABLE (1 << 4)
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#endif /* SOUTHBRIDGE_AMD_CS5530_CS5530_H */
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