coreboot-kgpe-d16/src/soc/amd
Felix Held bd9ab06808 vc/amd/fsp/morgana/FspmUpd: don't use pointers for usb_phy config
The size of a pointer changes between a 32 and 64 bit coreboot build. In
order to be able to use a 32 bit FSP in a 64 bit coreboot build, change
the pointer in the UPDs to a uint32_t to always have a 32 bit field in
the UPD for this. Also make sure that the address of the lcl_usb_phy
struct is located below the 4GB boundary, so that the truncation to 32
bits won't result in pointing to a different memory location than
intended. In this error case, which I don't expect to happen, print an
error and write 0 to mcfg->usb_phy_ptr so that the FSP will use its
default values.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1394aa6ef5f401e0c7bdd4861f1e28ae46e56e4f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70505
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12 01:26:03 +00:00
..
cezanne vc/amd/fsp/cezanne/FspmUpd: don't use pointers for usb_phy configuration 2022-12-08 18:01:38 +00:00
common treewide: Include <device/mmio.h> instead of <arch/mmio.h> 2022-12-10 05:07:14 +00:00
glinda sb,soc/amd: Remove unused southbridge_io_trap_handler() 2022-12-06 23:24:48 +00:00
mendocino soc/amd/mendocino: Enable LPC SPI DMA 2022-12-09 16:48:01 +00:00
morgana vc/amd/fsp/morgana/FspmUpd: don't use pointers for usb_phy config 2022-12-12 01:26:03 +00:00
picasso treewide: Include <device/mmio.h> instead of <arch/mmio.h> 2022-12-10 05:07:14 +00:00
stoneyridge sb,soc/amd: Remove unused southbridge_io_trap_handler() 2022-12-06 23:24:48 +00:00