6b5bc77c9b
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
40 lines
1.1 KiB
C
40 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <device/mmio.h>
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#include <device/pci_ops.h>
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#include "pch.h"
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#include "cpu/intel/model_2065x/model_2065x.h"
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#include <cpu/x86/msr.h>
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/* Early thermal init, must be done prior to giving ME its memory
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which is done at the end of raminit. */
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void early_thermal_init(void)
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{
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pci_devfn_t dev;
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msr_t msr;
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dev = PCI_DEV(0x0, 0x1f, 0x6);
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/* Program address for temporary BAR. */
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pci_write_config32(dev, 0x40, 0x40000000);
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pci_write_config32(dev, 0x44, 0x0);
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/* Activate temporary BAR. */
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pci_write_config32(dev, 0x40,
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pci_read_config32(dev, 0x40) | 5);
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/* Perform init. */
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/* Configure TJmax. */
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msr = rdmsr(MSR_TEMPERATURE_TARGET);
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write16((u16 *)0x40000012, ((msr.lo >> 16) & 0xff) << 6);
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/* Northbridge temperature slope and offset. */
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write16((u16 *)0x40000016, 0x7746);
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/* Enable thermal data reporting, processor, PCH and northbridge. */
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write16((u16 *)0x4000001a,
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(read16((u16 *)0x4000001a) & ~0xf) | 0x10f0);
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/* Disable temporary BAR. */
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pci_write_config32(dev, 0x40,
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pci_read_config32(dev, 0x40) & ~1);
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pci_write_config32(dev, 0x40, 0);
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}
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