coreboot-kgpe-d16/src
Angel Pons 12baf2057c soc/intel/baytrail/lpe.c: Align with Braswell
This reduces the differences between Bay Trail and Braswell.

Tested with BUILD_TIMELESS=1, Google Ninja remains identical.

Change-Id: If75b4299918f5bee3cc68bc662d03f1a819aef68
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43194
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25 10:21:59 +00:00
..
acpi src: Use ACPI macros 2020-07-21 18:26:47 +00:00
arch src: Make HAVE_CF9_RESET set the FADT reset register 2020-07-20 13:23:13 +00:00
commonlib src: Remove unused 'include <stdint.h> 2020-07-14 16:11:10 +00:00
console
cpu cpu/intel/model_1067x: Drop <cpu/x86/mp.h> include 2020-07-14 16:15:09 +00:00
device device/pci_device.c: Do not complain about disabled devices 2020-07-24 23:12:07 +00:00
drivers drivers/intel/gma/Kconfig: Avoid dependency hell when ignoring straps 2020-07-20 17:13:22 +00:00
ec ec/system76_ec: add support for System76 EC 2020-07-23 09:30:22 +00:00
include src/include/ramdetect.h: Add missing includes 2020-07-25 01:25:57 +00:00
lib src: Remove unused 'include <types.h>' 2020-07-14 16:10:17 +00:00
mainboard mb/intel/cedarisland: undo set trig and bufdis for NF pads 2020-07-25 10:19:18 +00:00
northbridge nb/intel/ironlake/raminit.c: initialize 'reply.command' 2020-07-25 01:23:49 +00:00
security security/intel/stm: Add missing <stdbool.h> 2020-07-21 20:04:12 +00:00
soc soc/intel/baytrail/lpe.c: Align with Braswell 2020-07-25 10:21:59 +00:00
southbridge sb/intel/bd82x6x: Use common irqlinks.asl 2020-07-25 00:12:06 +00:00
superio superio/common: Avoid NULL pointer dereference 2020-07-24 21:21:09 +00:00
vendorcode vc/amd/fsp/picasso: update UPD header 2020-07-24 20:29:11 +00:00
Kconfig arch/x86: Remove RELOCATABLE_RAMSTAGE 2020-07-06 06:17:47 +00:00