7449b625f8
The struct definition makes use of types defined in that header. Change-Id: I1d989298b8bf6266905330491c136874be7f5e28 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41475 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
166 lines
3.9 KiB
C
166 lines
3.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef INTEL_LYNXPOINT_LP_GPIO_H
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#define INTEL_LYNXPOINT_LP_GPIO_H
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#include <stdint.h>
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/* LynxPoint LP GPIOBASE Registers */
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#define GPIO_OWNER(set) (0x00 + ((set) * 4))
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#define GPIO_PIRQ_APIC_EN 0x10
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#define GPIO_BLINK 0x18
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#define GPIO_SER_BLINK 0x1c
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#define GPIO_SER_BLINK_CS 0x20
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#define GPIO_SER_BLINK_DATA 0x24
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#define GPIO_ROUTE(set) (0x30 + ((set) * 4))
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#define GPIO_RESET(set) (0x60 + ((set) * 4))
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#define GPIO_GLOBAL_CONFIG 0x7c
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#define GPIO_IRQ_IS(set) (0x80 + ((set) * 4))
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#define GPIO_IRQ_IE(set) (0x90 + ((set) * 4))
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#define GPIO_CONFIG0(gpio) (0x100 + ((gpio) * 8))
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#define GPIO_CONFIG1(gpio) (0x104 + ((gpio) * 8))
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#define MAX_GPIO_NUMBER 94 /* zero based */
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#define GPIO_LIST_END 0xffffffff
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/* conf0 */
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#define GPIO_MODE_NATIVE (0 << 0)
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#define GPIO_MODE_GPIO (1 << 0)
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#define GPIO_DIR_OUTPUT (0 << 2)
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#define GPIO_DIR_INPUT (1 << 2)
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#define GPIO_NO_INVERT (0 << 3)
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#define GPIO_INVERT (1 << 3)
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#define GPIO_IRQ_EDGE (0 << 4)
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#define GPIO_IRQ_LEVEL (1 << 4)
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#define GPI_LEVEL (1 << 30)
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#define GPO_LEVEL_SHIFT 31
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#define GPO_LEVEL_MASK (1UL << GPO_LEVEL_SHIFT)
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#define GPO_LEVEL_LOW (0UL << GPO_LEVEL_SHIFT)
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#define GPO_LEVEL_HIGH (1UL << GPO_LEVEL_SHIFT)
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/* conf1 */
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#define GPIO_PULL_NONE (0 << 0)
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#define GPIO_PULL_DOWN (1 << 0)
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#define GPIO_PULL_UP (2 << 0)
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#define GPIO_SENSE_ENABLE (0 << 2)
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#define GPIO_SENSE_DISABLE (1 << 2)
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/* owner */
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#define GPIO_OWNER_ACPI 0
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#define GPIO_OWNER_GPIO 1
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/* route */
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#define GPIO_ROUTE_SCI 0
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#define GPIO_ROUTE_SMI 1
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/* irqen */
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#define GPIO_IRQ_DISABLE 0
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#define GPIO_IRQ_ENABLE 1
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/* blink */
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#define GPO_NO_BLINK 0
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#define GPO_BLINK 1
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/* reset */
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#define GPIO_RESET_PWROK 0
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#define GPIO_RESET_RSMRST 1
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/* pirq route to io-apic */
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#define GPIO_PIRQ_APIC_MASK 0
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#define GPIO_PIRQ_APIC_ROUTE 1
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#define LP_GPIO_END \
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{ .conf0 = GPIO_LIST_END }
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#define LP_GPIO_NATIVE \
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{ .conf0 = GPIO_MODE_NATIVE }
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#define LP_GPIO_UNUSED \
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{ .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, \
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.owner = GPIO_OWNER_GPIO, \
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.conf1 = GPIO_SENSE_DISABLE }
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#define LP_GPIO_ACPI_SCI \
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{ .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, \
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.owner = GPIO_OWNER_ACPI, \
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.route = GPIO_ROUTE_SCI }
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#define LP_GPIO_ACPI_SMI \
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{ .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, \
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.owner = GPIO_OWNER_ACPI, \
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.route = GPIO_ROUTE_SMI }
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#define LP_GPIO_INPUT \
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{ .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, \
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.owner = GPIO_OWNER_GPIO }
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#define LP_GPIO_INPUT_INVERT \
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{ .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, \
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.owner = GPIO_OWNER_GPIO }
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#define LP_GPIO_IRQ_EDGE \
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{ .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_EDGE, \
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.owner = GPIO_OWNER_GPIO, \
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.irqen = GPIO_IRQ_ENABLE }
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#define LP_GPIO_IRQ_LEVEL \
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{ .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, \
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.owner = GPIO_OWNER_GPIO, \
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.irqen = GPIO_IRQ_ENABLE }
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#define LP_GPIO_PIRQ \
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{ .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, \
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.owner = GPIO_OWNER_GPIO, \
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.pirq = GPIO_PIRQ_APIC_ROUTE }
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#define LP_GPIO_OUT_HIGH \
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{ .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_HIGH, \
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.owner = GPIO_OWNER_GPIO, \
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.conf1 = GPIO_SENSE_DISABLE }
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#define LP_GPIO_OUT_LOW \
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{ .conf0 = GPIO_MODE_GPIO | GPIO_DIR_OUTPUT | GPO_LEVEL_LOW, \
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.owner = GPIO_OWNER_GPIO, \
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.conf1 = GPIO_SENSE_DISABLE }
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struct pch_lp_gpio_map {
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u8 gpio;
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u32 conf0;
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u32 conf1;
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u8 owner;
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u8 route;
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u8 irqen;
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u8 reset;
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u8 blink;
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u8 pirq;
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} __packed;
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/* Configure GPIOs with mainboard provided settings */
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void setup_pch_lp_gpios(const struct pch_lp_gpio_map map[]);
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/* get GPIO pin value */
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int get_gpio(int gpio_num);
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/*
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* get a number comprised of multiple GPIO values. gpio_num_array points to
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* the array of gpio pin numbers to scan, terminated by -1.
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*/
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unsigned int get_gpios(const int *gpio_num_array);
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void set_gpio(int gpio_num, int value);
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int gpio_is_native(int gpio_num);
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#endif
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