bdcccc0b88
Change-Id: I110974f3161f2991536df50acdfe32f68bd2cc60 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42850 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
86 lines
3 KiB
C
86 lines
3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef SOUTHBRIDGE_INTEL_LYNXPOINT_NVS_H
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#define SOUTHBRIDGE_INTEL_LYNXPOINT_NVS_H
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#include <commonlib/helpers.h>
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#include <stdint.h>
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#include "vendorcode/google/chromeos/gnvs.h"
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struct __packed global_nvs {
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/* Miscellaneous */
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u16 osys; /* 0x00 - Operating System */
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u8 smif; /* 0x02 - SMI function call ("TRAP") */
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u8 prm0; /* 0x03 - SMI function call parameter */
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u8 prm1; /* 0x04 - SMI function call parameter */
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u8 scif; /* 0x05 - SCI function call (via _L00) */
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u8 prm2; /* 0x06 - SCI function call parameter */
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u8 prm3; /* 0x07 - SCI function call parameter */
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u8 lckf; /* 0x08 - Global Lock function for EC */
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u8 prm4; /* 0x09 - Lock function parameter */
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u8 prm5; /* 0x0a - Lock function parameter */
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u32 p80d; /* 0x0b - Debug port (IO 0x80) value */
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u8 lids; /* 0x0f - LID state (open = 1) */
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u8 pwrs; /* 0x10 - Power state (AC = 1) */
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/* Thermal policy */
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u8 tlvl; /* 0x11 - Throttle Level Limit */
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u8 flvl; /* 0x12 - Current FAN Level */
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u8 tcrt; /* 0x13 - Critical Threshold */
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u8 tpsv; /* 0x14 - Passive Threshold */
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u8 tmax; /* 0x15 - CPU Tj_max */
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u8 f0of; /* 0x16 - FAN 0 OFF Threshold */
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u8 f0on; /* 0x17 - FAN 0 ON Threshold */
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u8 f0pw; /* 0x18 - FAN 0 PWM value */
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u8 f1of; /* 0x19 - FAN 1 OFF Threshold */
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u8 f1on; /* 0x1a - FAN 1 ON Threshold */
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u8 f1pw; /* 0x1b - FAN 1 PWM value */
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u8 f2of; /* 0x1c - FAN 2 OFF Threshold */
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u8 f2on; /* 0x1d - FAN 2 ON Threshold */
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u8 f2pw; /* 0x1e - FAN 2 PWM value */
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u8 f3of; /* 0x1f - FAN 3 OFF Threshold */
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u8 f3on; /* 0x20 - FAN 3 ON Threshold */
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u8 f3pw; /* 0x21 - FAN 3 PWM value */
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u8 f4of; /* 0x22 - FAN 4 OFF Threshold */
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u8 f4on; /* 0x23 - FAN 4 ON Threshold */
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u8 f4pw; /* 0x24 - FAN 4 PWM value */
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u8 tmps; /* 0x25 - Temperature Sensor ID */
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u8 rsvd3[2];
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/* Processor Identification */
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u8 apic; /* 0x28 - APIC enabled */
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u8 mpen; /* 0x29 - MP capable/enabled */
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u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */
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u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */
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u8 ppcm; /* 0x2c - Max. PPC state */
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u8 pcnt; /* 0x2d - Processor Count */
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u8 rsvd4[4];
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/* Super I/O & CMOS config */
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u8 natp; /* 0x32 - SIO type */
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u8 s5u0; /* 0x33 - Enable USB0 in S5 */
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u8 s5u1; /* 0x34 - Enable USB1 in S5 */
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u8 s3u0; /* 0x35 - Enable USB0 in S3 */
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u8 s3u1; /* 0x36 - Enable USB1 in S3 */
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u8 s33g; /* 0x37 - Enable S3 in 3G */
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u32 obsolete_cmem; /* 0x38 - CBMEM TOC */
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/* Integrated Graphics Device */
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u8 igds; /* 0x3c - IGD state */
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u8 tlst; /* 0x3d - Display Toggle List Pointer */
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u8 cadl; /* 0x3e - currently attached devices */
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u8 padl; /* 0x3f - previously attached devices */
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u8 rsvd14[27];
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/* TPM support */
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u8 tpmp; /* 0x5b - TPM Present */
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u8 tpme; /* 0x5c - TPM Enable */
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u8 rsvd5[3];
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/* LynxPoint Serial IO device BARs */
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u32 s0b[8]; /* 0x60 - 0x7f - BAR0 */
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u32 s1b[8]; /* 0x80 - 0x9f - BAR1 */
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u32 cbmc; /* 0xa0 - 0xa3 - coreboot memconsole */
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u8 rsvd6[92];
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/* ChromeOS specific (starts at 0x100)*/
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chromeos_acpi_t chromeos;
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};
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check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
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#endif /* SOUTHBRIDGE_INTEL_LYNXPOINT_NVS_H */
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