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Max Blau 13bfd04a99 superio/fintek/f71808a: Add more optional ramstage registers
Add more registers and make them optional, so they keep untouched/
their default if omitted.

Change-Id: I5d8008176d2972976b387c558658b8e70b50af8e
Signed-off-by: Max Blau <tripleshiftone@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-05-01 00:09:57 +00:00
3rdparty 3rdparty/fsp: Update submodule pointer to upstream master 2019-04-25 15:52:53 +00:00
Documentation Documentation: Add FIT 2019-04-30 08:18:57 +00:00
configs configs: Add a target to buildtest the ivybridge mrc.bin bootpath 2019-04-23 10:18:44 +00:00
payloads payloads/seabios: Update the stable git hash of 1.12.1 2019-04-24 10:21:59 +00:00
src superio/fintek/f71808a: Add more optional ramstage registers 2019-05-01 00:09:57 +00:00
util util/sconfig: Throw an error if override tree has no devices 2019-04-24 16:23:51 +00:00
.checkpatch.conf .checkpatch.conf: Ignore a few more warnings 2018-08-13 12:23:24 +00:00
.clang-format Revert "lint/clang-format: set to 96 chars per line" 2019-03-15 23:05:06 +00:00
.gitignore util/bucts: Add tool to manipulate BUC.TS bit on Intel targets 2018-11-19 08:19:16 +00:00
.gitmodules 3rdparty/opensbi: Add submodule 2019-04-24 08:46:25 +00:00
.gitreview
COPYING
MAINTAINERS MAINTAINERS: Update Braswell SoC maintainers 2019-03-06 20:05:11 +00:00
Makefile Hook up Kconfig Ada spec file 2019-02-06 16:20:35 +00:00
Makefile.inc Makefile: Check for errors in ACPI decompilation, too 2019-04-29 12:15:15 +00:00
README.md README: Convert to Markdown 2018-09-16 13:01:58 +00:00
gnat.adc
toolchain.inc arch/power8: Rename to ppc64 2018-11-30 20:02:17 +00:00

README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.