13f1c2af8b
1. x86_setup_mtrr take address bit.
2. generic ht, pcix, pcie beidge...
3. scan bus and reset_bus
4. ht read ctrl to decide if the ht chain
is ready
5. Intel e7520 and e7525 support
6. new ich5r support
7. intel sb 6300 support.
yhlu patch
1. split x86_setup_mtrrs to fixed and var
2. if (resource->flags & IORESOURCE_FIXED ) return; in device.c pick_largest_resource
3. in_conherent.c K8_SCAN_PCI_BUS
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
463 lines
20 KiB
C
463 lines
20 KiB
C
#include <console/console.h>
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#include <arch/smp/mpspec.h>
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#include <device/pci.h>
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#include <string.h>
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#include <stdint.h>
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#if CONFIG_LOGICAL_CPUS==1
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#include <cpu/amd/dualcore.h>
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#endif
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static unsigned node_link_to_bus(unsigned node, unsigned link)
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{
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device_t dev;
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unsigned reg;
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dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
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if (!dev) {
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return 0;
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}
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for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
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uint32_t config_map;
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unsigned dst_node;
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unsigned dst_link;
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unsigned bus_base;
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config_map = pci_read_config32(dev, reg);
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if ((config_map & 3) != 3) {
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continue;
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}
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dst_node = (config_map >> 4) & 7;
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dst_link = (config_map >> 8) & 3;
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bus_base = (config_map >> 16) & 0xff;
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#if 0
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printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
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dst_node, dst_link, bus_base,
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reg, config_map);
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#endif
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if ((dst_node == node) && (dst_link == link))
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{
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return bus_base;
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}
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}
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return 0;
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}
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void *smp_write_config_table(void *v)
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{
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static const char sig[4] = "PCMP";
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static const char oem[8] = "TYAN ";
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static const char productid[12] = "S2895 ";
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struct mp_config_table *mc;
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unsigned char bus_num;
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unsigned char bus_isa;
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unsigned char bus_ck804_0; //1
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unsigned char bus_ck804_1; //2
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unsigned char bus_ck804_2; //3
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unsigned char bus_ck804_3; //4
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unsigned char bus_ck804_4; //5
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unsigned char bus_ck804_5; //6
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unsigned char bus_8131_0; //7
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unsigned char bus_8131_1; //8
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unsigned char bus_8131_2; //9
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unsigned char bus_ck804b_0;//a
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unsigned char bus_ck804b_1;//b
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unsigned char bus_ck804b_2;//c
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unsigned char bus_ck804b_3;//d
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unsigned char bus_ck804b_4;//e
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unsigned char bus_ck804b_5;//f
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unsigned apicid_base;
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unsigned apicid_ck804;
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unsigned apicid_8131_1;
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unsigned apicid_8131_2;
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unsigned apicid_ck804b;
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mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
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memset(mc, 0, sizeof(*mc));
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memcpy(mc->mpc_signature, sig, sizeof(sig));
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mc->mpc_length = sizeof(*mc); /* initially just the header */
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mc->mpc_spec = 0x04;
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mc->mpc_checksum = 0; /* not yet computed */
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memcpy(mc->mpc_oem, oem, sizeof(oem));
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memcpy(mc->mpc_productid, productid, sizeof(productid));
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mc->mpc_oemptr = 0;
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mc->mpc_oemsize = 0;
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mc->mpc_entry_count = 0; /* No entries yet... */
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mc->mpc_lapic = LAPIC_ADDR;
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mc->mpe_length = 0;
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mc->mpe_checksum = 0;
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mc->reserved = 0;
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smp_write_processors(mc);
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{
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device_t dev;
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bus_ck804_0 = node_link_to_bus(0, 0);
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if (bus_ck804_0 == 0) {
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printk_debug("ERROR - cound not find bus for node 0 chain 0, using defaults\n");
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bus_ck804_0 = 1;
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}
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/* CK804 */
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dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x09,0));
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if (dev) {
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bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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#if 0
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bus_ck804_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
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bus_ck804_2++;
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#else
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bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
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bus_ck804_5++;
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#endif
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}
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else {
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printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", CK804_DEVN_BASE + 0x09);
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bus_ck804_1 = 2;
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#if 0
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bus_ck804_2 = 3;
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#else
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bus_ck804_5 = 3;
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#endif
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}
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#if 0
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dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0b,0));
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if (dev) {
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bus_ck804_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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bus_ck804_3 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
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bus_ck804_3++;
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}
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else {
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printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", CK804_DEVN_BASE + 0x0b);
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bus_ck804_3 = bus_ck804_2+1;
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}
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dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0c,0));
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if (dev) {
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bus_ck804_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
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bus_ck804_4++;
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}
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else {
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printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", CK804_DEVN_BASE + 0x0c);
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bus_ck804_4 = bus_ck804_3+1;
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}
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dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0d,0));
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if (dev) {
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bus_ck804_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
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bus_ck804_5++;
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}
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else {
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printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n",CK804_DEVN_BASE + 0x0d);
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bus_ck804_5 = bus_ck804_4+1;
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}
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#endif
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dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0e,0));
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if (dev) {
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bus_ck804_5 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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bus_8131_0 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
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bus_8131_0++;
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}
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else {
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printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n",CK804_DEVN_BASE + 0x0e);
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bus_8131_0 = bus_ck804_5+1;
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}
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/* 8131-1 */
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dev = dev_find_slot(bus_8131_0, PCI_DEVFN(0x01,0));
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if (dev) {
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bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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bus_8131_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
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bus_8131_2++;
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}
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else {
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printk_debug("ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0);
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bus_8131_1 = bus_8131_0+1;
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bus_8131_2 = bus_8131_0+2;
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}
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/* 8131-2 */
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dev = dev_find_slot(bus_8131_0, PCI_DEVFN(0x02,0));
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if (dev) {
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bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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bus_ck804b_0 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
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bus_ck804b_0++;
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}
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else {
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printk_debug("ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0);
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bus_8131_2 = bus_8131_1+1;
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bus_ck804b_0 = bus_8131_1+2;
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}
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/* CK804b */
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#if 0
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dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(CK804_DEVN_BASE + 0x09,0));
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if (dev) {
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bus_ck804b_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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bus_ck804b_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
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bus_ck804b_2++;
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}
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else {
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printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,CK804_DEVN_BASE+0x09);
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bus_ck804b_1 = bus_ck804b_0+1;
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bus_ck804b_2 = bus_ck804b_0+2;
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}
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dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0b,0));
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if (dev) {
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bus_ck804b_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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bus_ck804b_3 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
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bus_ck804b_3++;
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}
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else {
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printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,CK804_DEVN_BASE+0x0b);
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bus_ck804b_2 = bus_ck804b_0+1;
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bus_ck804b_3 = bus_ck804b_0+2;
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}
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dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0c,0));
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if (dev) {
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bus_ck804b_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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bus_ck804b_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
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bus_ck804b_4++;
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}
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else {
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printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,CK804_DEVN_BASE+0x0c);
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bus_ck804b_4 = bus_ck804b_3+1;
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}
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dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0d,0));
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if (dev) {
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bus_ck804b_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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bus_ck804b_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
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bus_ck804b_5++;
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}
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else {
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printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,CK804_DEVN_BASE+0x0d);
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bus_ck804b_5 = bus_ck804b_4+1;
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}
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#endif
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dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0e,0));
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if (dev) {
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bus_ck804b_5 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
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bus_isa++;
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}
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else {
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printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,CK804_DEVN_BASE+0x0e);
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#if 1
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bus_ck804b_5 = bus_ck804b_0+1;
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#endif
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bus_isa = bus_ck804b_5+1;
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}
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}
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/*Bus: Bus ID Type*/
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/* define bus and isa numbers */
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for(bus_num = 0; bus_num < bus_isa; bus_num++) {
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smp_write_bus(mc, bus_num, "PCI ");
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}
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smp_write_bus(mc, bus_isa, "ISA ");
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/*I/O APICs: APIC ID Version State Address*/
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#if CONFIG_LOGICAL_CPUS==1
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apicid_base = get_apicid_base(4);
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#else
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apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
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#endif
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apicid_ck804 = apicid_base;
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apicid_8131_1 = apicid_base+1;
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apicid_8131_2 = apicid_base+2;
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apicid_ck804b = apicid_base+3;
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// smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
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{
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device_t dev;
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struct resource *res;
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uint32_t dword;
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dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE+ 0x1,0));
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if (dev) {
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res = find_resource(dev, PCI_BASE_ADDRESS_1);
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if (res) {
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smp_write_ioapic(mc, apicid_ck804, 0x11, res->base);
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}
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dword = 0x0000d218;
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pci_write_config32(dev, 0x7c, dword);
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dword = 0x12008a00;
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pci_write_config32(dev, 0x80, dword);
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dword = 0x00080d7d;
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pci_write_config32(dev, 0x84, dword);
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}
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dev = dev_find_slot(bus_8131_0, PCI_DEVFN(0x1,1));
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if (dev) {
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res = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (res) {
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smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
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}
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}
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dev = dev_find_slot(bus_8131_0, PCI_DEVFN(0x2,1));
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if (dev) {
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res = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (res) {
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smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
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}
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}
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dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(CK804_DEVN_BASE + 0x1,0));
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if (dev) {
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res = find_resource(dev, PCI_BASE_ADDRESS_1);
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if (res) {
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smp_write_ioapic(mc, apicid_ck804b, 0x11, res->base);
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}
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dword = 0x0000d218;
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pci_write_config32(dev, 0x7c, dword);
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dword = 0x00000000;
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pci_write_config32(dev, 0x80, dword);
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dword = 0x00000d00;
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pci_write_config32(dev, 0x84, dword);
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}
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}
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/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#
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*/ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_ck804, 0x0);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_ck804, 0x1);
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smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_ck804, 0x2);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, apicid_ck804, 0x3);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, apicid_ck804, 0x4);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, apicid_ck804, 0x6);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x7, apicid_ck804, 0x7);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x8, apicid_ck804, 0x8);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, apicid_ck804, 0xc);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, apicid_ck804, 0xd);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_ck804, 0xe);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_ck804, 0xf);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+1)<<2)|1, apicid_ck804, 0xa);
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// 10
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+2)<<2)|0, apicid_ck804, 0x15); // 21
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+2)<<2)|1, apicid_ck804, 0x14); // 20
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+4)<<2)|0, apicid_ck804, 0x14); // 20
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +7)<<2)|0, apicid_ck804, 0x17); // 23
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +8)<<2)|0, apicid_ck804, 0x16); // 22
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +0x0a)<<2)|0, apicid_ck804, 0x15); // 21
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#if CK804_DEVN_BASE == 0
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|0, apicid_ck804, 0x12); // 18
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|1, apicid_ck804, 0x13); // 19
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|2, apicid_ck804, 0x10); // 16
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|3, apicid_ck804, 0x11); // 17
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#else
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|0, apicid_ck804, 0x11); // 17
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|1, apicid_ck804, 0x12); // 18
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|2, apicid_ck804, 0x13); // 19
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|3, apicid_ck804, 0x10); // 16
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#endif
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x05<<2)|0, apicid_ck804, 0x13); // 19
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|0, apicid_ck804, 0x10); // 16
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|1, apicid_ck804, 0x11); // 17
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|2, apicid_ck804, 0x12); // 18
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|3, apicid_ck804, 0x13); // 19
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_0, ((CK804_DEVN_BASE+0x0a)<<2)|0, apicid_ck804b, 0x15);//24+4+4+21=53
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#if CK804_DEVN_BASE == 0
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|0, apicid_ck804b, 0x12);//18+24+4+4=50
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|1, apicid_ck804b, 0x13); // 19
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|2, apicid_ck804b, 0x10); // 16
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|3, apicid_ck804b, 0x11); // 17
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#else
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|0, apicid_ck804b, 0x11);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|1, apicid_ck804b, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|2, apicid_ck804b, 0x13);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|3, apicid_ck804b, 0x10);
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#endif
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//Channel B of 8131
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//Slot 4 PCI-X 100/66
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|0, apicid_8131_2, 0x0); //24+4 = 28
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|1, apicid_8131_2, 0x1);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|2, apicid_8131_2, 0x2); //
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|3, apicid_8131_2, 0x3); //
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//Slot 5 PCIX 100/66
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|0, apicid_8131_2, 0x1); //24+4+1 = 29
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|1, apicid_8131_2, 0x2);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|2, apicid_8131_2, 0x3);//
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|3, apicid_8131_2, 0x0);//
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//OnBoard LSI SCSI
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|0, apicid_8131_2, 0x2); // 24+4+2 = 30
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|1, apicid_8131_2, 0x3); // 31
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|
|
|
//Channel A of 8131
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|
|
|
//Slot 6 PCIX 133/100/66
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|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|0, apicid_8131_1, 0x0); // 24
|
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|1, apicid_8131_1, 0x1);//
|
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|2, apicid_8131_1, 0x2);//
|
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|3, apicid_8131_1, 0x3);//
|
|
|
|
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
|
|
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
|
|
smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
|
|
/* There is no extension information... */
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|
|
|
/* Compute the checksums */
|
|
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
|
|
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
|
|
printk_debug("Wrote the mp table end at: %p - %p\n",
|
|
mc, smp_next_mpe_entry(mc));
|
|
return smp_next_mpe_entry(mc);
|
|
}
|
|
|
|
unsigned long write_smp_table(unsigned long addr)
|
|
{
|
|
void *v;
|
|
v = smp_write_floating_table(addr);
|
|
return (unsigned long)smp_write_config_table(v);
|
|
}
|