ce6c35699b
For the rails controllable by the host processor through gpios turn them off in the sleep paths. The result is that S3 and S5 will turn off those rails. BUG=chrome-os-partner:47228 BRANCH=None TEST=Built and booted glados. Suspended and resumed. Change-Id: I6d45683b64ca5f7c3c47e11f95951bd2d9abf31e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ed432e2b5535da6f872a53b76886d983f00b4e8e Original-Change-Id: I94d7e0b00bf7e7da8dc59f299e41b72e8fcb64f4 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/312320 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/12445 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
152 lines
3.4 KiB
C
152 lines
3.4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2015 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <cpu/x86/smm.h>
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#include <elog.h>
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#include <ec/google/chromeec/ec.h>
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#include <gpio.h>
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#include <soc/iomap.h>
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#include <soc/nvs.h>
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#include <soc/pm.h>
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#include <soc/smm.h>
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#include "ec.h"
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#include "gpio.h"
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int mainboard_io_trap_handler(int smif)
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{
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switch (smif) {
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case 0x99:
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printk(BIOS_DEBUG, "Sample\n");
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smm_get_gnvs()->smif = 0;
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break;
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default:
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return 0;
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}
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/* On success, the IO Trap Handler returns 0
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* On failure, the IO Trap Handler returns a value != 0
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*
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* For now, we force the return value to 0 and log all traps to
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* see what's going on.
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*/
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return 1;
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}
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static u8 mainboard_smi_ec(void)
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{
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u8 cmd = 0;
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#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
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u32 pm1_cnt;
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cmd = google_chromeec_get_event();
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/* Log this event */
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if (IS_ENABLED(CONFIG_ELOG_GSMI) && cmd)
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elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);
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switch (cmd) {
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case EC_HOST_EVENT_LID_CLOSED:
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printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
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/* Go to S5 */
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pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
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pm1_cnt |= (0xf << 10);
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outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT);
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break;
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}
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#endif
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return cmd;
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}
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void mainboard_smi_gpi_handler(const struct gpi_status *sts)
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{
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if (gpi_status_get(sts, EC_SMI_GPI)) {
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/* Process all pending events */
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while (mainboard_smi_ec() != 0)
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;
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}
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}
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static void google_ec_smi_sleep(u8 slp_typ)
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{
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switch (slp_typ) {
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case 3:
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/* Enable wake events */
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google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
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break;
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case 5:
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/* Enable wake events */
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google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);
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break;
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}
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/* Disable SCI and SMI events */
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google_chromeec_set_smi_mask(0);
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google_chromeec_set_sci_mask(0);
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/* Clear pending events that may trigger immediate wake */
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while (google_chromeec_get_event() != 0)
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;
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}
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static void mainboard_gpio_smi_sleep(u8 slp_typ)
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{
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int i;
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/* Power down the rails on any sleep type. */
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gpio_t active_high_signals[] = {
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EN_PP3300_KEPLER,
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EN_PP3300_DX_TOUCH,
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EN_PP3300_DX_EMMC,
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EN_PP1800_DX_EMMC,
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EN_PP3300_DX_CAM,
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};
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for (i = 0; i < ARRAY_SIZE(active_high_signals); i++)
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gpio_set(active_high_signals[i], 0);
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}
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void mainboard_smi_sleep(u8 slp_typ)
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{
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if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
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google_ec_smi_sleep(slp_typ);
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mainboard_gpio_smi_sleep(slp_typ);
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}
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int mainboard_smi_apmc(u8 apmc)
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{
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#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
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switch (apmc) {
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case APM_CNT_ACPI_ENABLE:
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google_chromeec_set_smi_mask(0);
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/* Clear all pending events */
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while (google_chromeec_get_event() != 0)
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;
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google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
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break;
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case APM_CNT_ACPI_DISABLE:
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google_chromeec_set_sci_mask(0);
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/* Clear all pending events */
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while (google_chromeec_get_event() != 0)
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;
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google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);
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break;
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}
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#endif
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return 0;
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}
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