coreboot-kgpe-d16/src/include/reset.h
Martin Roth 239b5df268 include: Add SPDX-License-Identifiers to files missing them
This adds SPDX-License-Identifiers to all of the files in src/include
that are missing them or have unrecognized identifiers.

Files that were written specifically for coreboot and don't have license
information are licensed GPL-2.0-only, which is the license for the
overall coreboot project.

Files that were sourced from Linux are similarly GPL-2.0-only.

The cpu/power files were committed with source that was licensed as
GPL-2.0-or-later, so presumably that's the license for that entire
commit.

The final file, vbe.h gives a pointer to the BSD-2-Clause license
at opensource.org.

Change-Id: I3f8fd7848ce11c1a0060e05903fb17a7583b4725
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-08-01 13:59:11 +00:00

44 lines
1.2 KiB
C

/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef RESET_H
#define RESET_H
/*
* Generic board reset function. Call from common code that
* wants to trigger a reset.
*/
__noreturn void board_reset(void);
/*
* SoC or board specific implementation of the board reset.
*
* Implementations shall meet the following criteria:
*
* o For vboot support, the TPM MUST be reset.
*
* o All SoC/chipset blocks SHOULD be reset except for those
* that are intentionally meant to survive reset (e.g. tomb-
* stone registers and that sort of stuff).
*
* o All external SoC pins SHOULD return to power-on reset values.
*
* o The CPU MUST resume execution from power-on reset vector
* (same as cold boot).
*
* o Other board components (e.g. PCI, SDIO and stuff) SHOULD
* be reset.
*
* o USB SHOULD be power-cycled.
*
* o Board components that are intended to be fully independent
* from SoC (e.g. EC and EC-attached devices, the Cr50 on
* Chromebooks) SHOULD NOT be reset.
*
* General recommendations:
*
* o DRAM SHOULD NOT lose power if possible.
*
* o Reset time SHOULD be minimized
*/
void do_board_reset(void);
#endif